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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-05 22:55:53 -04:00
Merge branch 'increase-maximum-mtu-to-9k-for-airoha-en7581-soc'
Lorenzo Bianconi says: ==================== Increase maximum MTU to 9k for Airoha EN7581 SoC EN7581 SoC supports 9k maximum MTU. Enable the reception of Scatter-Gather (SG) frames for Airoha EN7581. Introduce airoha_dev_change_mtu callback. ==================== Link: https://patch.msgid.link/20250304-airoha-eth-rx-sg-v1-0-283ebc61120e@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
@@ -138,15 +138,10 @@ static void airoha_fe_maccr_init(struct airoha_eth *eth)
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{
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int p;
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for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) {
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for (p = 1; p <= ARRAY_SIZE(eth->ports); p++)
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airoha_fe_set(eth, REG_GDM_FWD_CFG(p),
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GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM |
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GDM_DROP_CRC_ERR);
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airoha_fe_rmw(eth, REG_GDM_LEN_CFG(p),
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GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
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FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
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FIELD_PREP(GDM_LONG_LEN_MASK, 4004));
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}
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airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK,
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FIELD_PREP(CDM1_VLAN_MASK, 0x8100));
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@@ -620,10 +615,10 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
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struct airoha_qdma_desc *desc = &q->desc[q->tail];
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u32 hash, reason, msg1 = le32_to_cpu(desc->msg1);
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dma_addr_t dma_addr = le32_to_cpu(desc->addr);
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struct page *page = virt_to_head_page(e->buf);
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u32 desc_ctrl = le32_to_cpu(desc->ctrl);
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struct airoha_gdm_port *port;
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struct sk_buff *skb;
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int len, p;
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int data_len, len, p;
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if (!(desc_ctrl & QDMA_DESC_DONE_MASK))
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break;
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@@ -641,30 +636,41 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
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dma_sync_single_for_cpu(eth->dev, dma_addr,
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SKB_WITH_OVERHEAD(q->buf_size), dir);
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data_len = q->skb ? q->buf_size
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: SKB_WITH_OVERHEAD(q->buf_size);
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if (data_len < len)
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goto free_frag;
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p = airoha_qdma_get_gdm_port(eth, desc);
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if (p < 0 || !eth->ports[p]) {
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page_pool_put_full_page(q->page_pool,
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virt_to_head_page(e->buf),
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true);
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continue;
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}
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if (p < 0 || !eth->ports[p])
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goto free_frag;
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port = eth->ports[p];
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skb = napi_build_skb(e->buf, q->buf_size);
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if (!skb) {
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page_pool_put_full_page(q->page_pool,
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virt_to_head_page(e->buf),
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true);
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break;
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if (!q->skb) { /* first buffer */
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q->skb = napi_build_skb(e->buf, q->buf_size);
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if (!q->skb)
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goto free_frag;
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__skb_put(q->skb, len);
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skb_mark_for_recycle(q->skb);
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q->skb->dev = port->dev;
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q->skb->protocol = eth_type_trans(q->skb, port->dev);
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q->skb->ip_summed = CHECKSUM_UNNECESSARY;
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skb_record_rx_queue(q->skb, qid);
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} else { /* scattered frame */
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struct skb_shared_info *shinfo = skb_shinfo(q->skb);
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int nr_frags = shinfo->nr_frags;
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if (nr_frags >= ARRAY_SIZE(shinfo->frags))
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goto free_frag;
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skb_add_rx_frag(q->skb, nr_frags, page,
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e->buf - page_address(page), len,
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q->buf_size);
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}
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skb_reserve(skb, 2);
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__skb_put(skb, len);
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skb_mark_for_recycle(skb);
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skb->dev = port->dev;
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skb->protocol = eth_type_trans(skb, skb->dev);
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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skb_record_rx_queue(skb, qid);
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if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))
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continue;
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if (netdev_uses_dsa(port->dev)) {
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/* PPE module requires untagged packets to work
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@@ -677,22 +683,27 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
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if (sptag < ARRAY_SIZE(port->dsa_meta) &&
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port->dsa_meta[sptag])
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skb_dst_set_noref(skb,
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skb_dst_set_noref(q->skb,
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&port->dsa_meta[sptag]->dst);
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}
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hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1);
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if (hash != AIROHA_RXD4_FOE_ENTRY)
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skb_set_hash(skb, jhash_1word(hash, 0),
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skb_set_hash(q->skb, jhash_1word(hash, 0),
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PKT_HASH_TYPE_L4);
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reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1);
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if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
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airoha_ppe_check_skb(eth->ppe, hash);
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napi_gro_receive(&q->napi, skb);
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done++;
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napi_gro_receive(&q->napi, q->skb);
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q->skb = NULL;
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continue;
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free_frag:
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page_pool_put_full_page(q->page_pool, page, true);
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dev_kfree_skb(q->skb);
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q->skb = NULL;
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}
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airoha_qdma_fill_rx_queue(q);
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@@ -767,6 +778,7 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
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FIELD_PREP(RX_RING_THR_MASK, thr));
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airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
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FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head));
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airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK);
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airoha_qdma_fill_rx_queue(q);
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@@ -1166,7 +1178,6 @@ static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
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}
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airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG,
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GLOBAL_CFG_RX_2B_OFFSET_MASK |
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FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) |
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GLOBAL_CFG_CPU_TXR_RR_MASK |
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GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK |
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@@ -1520,9 +1531,9 @@ static void airoha_update_hw_stats(struct airoha_gdm_port *port)
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static int airoha_dev_open(struct net_device *dev)
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{
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int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN;
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struct airoha_gdm_port *port = netdev_priv(dev);
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struct airoha_qdma *qdma = port->qdma;
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int err;
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netif_tx_start_all_queues(dev);
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err = airoha_set_vip_for_gdm_port(port, true);
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@@ -1536,6 +1547,11 @@ static int airoha_dev_open(struct net_device *dev)
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airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
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GDM_STAG_EN_MASK);
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airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id),
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GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
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FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
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FIELD_PREP(GDM_LONG_LEN_MASK, len));
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airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
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GLOBAL_CFG_TX_DMA_EN_MASK |
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GLOBAL_CFG_RX_DMA_EN_MASK);
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@@ -1689,6 +1705,20 @@ static void airoha_dev_get_stats64(struct net_device *dev,
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} while (u64_stats_fetch_retry(&port->stats.syncp, start));
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}
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static int airoha_dev_change_mtu(struct net_device *dev, int mtu)
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{
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struct airoha_gdm_port *port = netdev_priv(dev);
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struct airoha_eth *eth = port->qdma->eth;
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u32 len = ETH_HLEN + mtu + ETH_FCS_LEN;
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airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id),
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GDM_LONG_LEN_MASK,
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FIELD_PREP(GDM_LONG_LEN_MASK, len));
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WRITE_ONCE(dev->mtu, mtu);
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return 0;
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}
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static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb,
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struct net_device *sb_dev)
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{
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@@ -2384,6 +2414,7 @@ static const struct net_device_ops airoha_netdev_ops = {
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.ndo_init = airoha_dev_init,
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.ndo_open = airoha_dev_open,
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.ndo_stop = airoha_dev_stop,
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.ndo_change_mtu = airoha_dev_change_mtu,
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.ndo_select_queue = airoha_dev_select_queue,
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.ndo_start_xmit = airoha_dev_xmit,
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.ndo_get_stats64 = airoha_dev_get_stats64,
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@@ -20,7 +20,7 @@
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#define AIROHA_MAX_DSA_PORTS 7
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#define AIROHA_MAX_NUM_RSTS 3
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#define AIROHA_MAX_NUM_XSI_RSTS 5
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#define AIROHA_MAX_MTU 2000
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#define AIROHA_MAX_MTU 9216
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#define AIROHA_MAX_PACKET_SIZE 2048
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#define AIROHA_NUM_QOS_CHANNELS 4
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#define AIROHA_NUM_QOS_QUEUES 8
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@@ -176,6 +176,7 @@ struct airoha_queue {
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struct napi_struct napi;
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struct page_pool *page_pool;
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struct sk_buff *skb;
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};
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struct airoha_tx_irq_queue {
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@@ -626,10 +626,15 @@
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#define REG_RX_DELAY_INT_IDX(_n) \
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(((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
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#define REG_RX_SCATTER_CFG(_n) \
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(((_n) < 16) ? 0x0214 + ((_n) << 5) : 0x0e14 + (((_n) - 16) << 5))
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#define RX_DELAY_INT_MASK GENMASK(15, 0)
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#define RX_RING_DMA_IDX_MASK GENMASK(15, 0)
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#define RX_RING_SG_EN_MASK BIT(0)
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#define REG_INGRESS_TRTCM_CFG 0x0070
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#define INGRESS_TRTCM_EN_MASK BIT(31)
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#define INGRESS_TRTCM_MODE_MASK BIT(30)
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