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i3c: mipi-i3c-hci: Consolidate common xfer processing logic
Several parts of the MIPI I3C HCI driver duplicate the same sequence for
queuing a transfer, waiting for completion, and handling timeouts. This
logic appears in five separate locations and will be affected by an
upcoming fix.
Refactor the repeated code into a new helper, i3c_hci_process_xfer(), and
store the timeout value in the hci_xfer structure so that callers do not
need to pass it as a separate parameter.
Fixes: 9ad9a52cce ("i3c/master: introduce the mipi-i3c-hci driver")
Cc: stable@vger.kernel.org
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260306072451.11131-12-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
committed by
Alexandre Belloni
parent
b6d586431a
commit
7ac45bc68f
@@ -331,12 +331,10 @@ static int hci_cmd_v1_daa(struct i3c_hci *hci)
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CMD_A0_ROC | CMD_A0_TOC;
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xfer->cmd_desc[1] = 0;
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xfer->completion = &done;
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hci->io->queue_xfer(hci, xfer, 1);
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if (!wait_for_completion_timeout(&done, HZ) &&
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hci->io->dequeue_xfer(hci, xfer, 1)) {
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ret = -ETIMEDOUT;
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xfer->timeout = HZ;
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ret = i3c_hci_process_xfer(hci, xfer, 1);
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if (ret)
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break;
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}
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if ((RESP_STATUS(xfer->response) == RESP_ERR_ADDR_HEADER ||
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RESP_STATUS(xfer->response) == RESP_ERR_NACK) &&
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RESP_DATA_LENGTH(xfer->response) == 1) {
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@@ -253,6 +253,7 @@ static int hci_cmd_v2_daa(struct i3c_hci *hci)
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xfer[0].rnw = true;
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xfer[0].cmd_desc[1] = CMD_A1_DATA_LENGTH(8);
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xfer[1].completion = &done;
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xfer[1].timeout = HZ;
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for (;;) {
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ret = i3c_master_get_free_addr(&hci->master, next_addr);
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@@ -272,12 +273,9 @@ static int hci_cmd_v2_daa(struct i3c_hci *hci)
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CMD_A0_ASSIGN_ADDRESS(next_addr) |
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CMD_A0_ROC |
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CMD_A0_TOC;
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hci->io->queue_xfer(hci, xfer, 2);
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if (!wait_for_completion_timeout(&done, HZ) &&
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hci->io->dequeue_xfer(hci, xfer, 2)) {
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ret = -ETIMEDOUT;
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ret = i3c_hci_process_xfer(hci, xfer, 2);
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if (ret)
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break;
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}
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if (RESP_STATUS(xfer[0].response) != RESP_SUCCESS) {
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ret = 0; /* no more devices to be assigned */
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break;
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@@ -213,6 +213,25 @@ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci)
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reg_write(DCT_SECTION, FIELD_PREP(DCT_TABLE_INDEX, 0));
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}
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int i3c_hci_process_xfer(struct i3c_hci *hci, struct hci_xfer *xfer, int n)
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{
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struct completion *done = xfer[n - 1].completion;
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unsigned long timeout = xfer[n - 1].timeout;
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int ret;
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ret = hci->io->queue_xfer(hci, xfer, n);
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if (ret)
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return ret;
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if (!wait_for_completion_timeout(done, timeout) &&
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hci->io->dequeue_xfer(hci, xfer, n)) {
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dev_err(&hci->master.dev, "%s: timeout error\n", __func__);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int i3c_hci_send_ccc_cmd(struct i3c_master_controller *m,
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struct i3c_ccc_cmd *ccc)
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{
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@@ -253,18 +272,14 @@ static int i3c_hci_send_ccc_cmd(struct i3c_master_controller *m,
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last = i - 1;
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xfer[last].cmd_desc[0] |= CMD_0_TOC;
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xfer[last].completion = &done;
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xfer[last].timeout = HZ;
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if (prefixed)
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xfer--;
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ret = hci->io->queue_xfer(hci, xfer, nxfers);
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ret = i3c_hci_process_xfer(hci, xfer, nxfers);
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if (ret)
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goto out;
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if (!wait_for_completion_timeout(&done, HZ) &&
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hci->io->dequeue_xfer(hci, xfer, nxfers)) {
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ret = -ETIMEDOUT;
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goto out;
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}
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for (i = prefixed; i < nxfers; i++) {
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if (ccc->rnw)
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ccc->dests[i - prefixed].payload.len =
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@@ -335,15 +350,11 @@ static int i3c_hci_i3c_xfers(struct i3c_dev_desc *dev,
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last = i - 1;
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xfer[last].cmd_desc[0] |= CMD_0_TOC;
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xfer[last].completion = &done;
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xfer[last].timeout = HZ;
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ret = hci->io->queue_xfer(hci, xfer, nxfers);
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ret = i3c_hci_process_xfer(hci, xfer, nxfers);
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if (ret)
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goto out;
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if (!wait_for_completion_timeout(&done, HZ) &&
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hci->io->dequeue_xfer(hci, xfer, nxfers)) {
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ret = -ETIMEDOUT;
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goto out;
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}
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for (i = 0; i < nxfers; i++) {
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if (i3c_xfers[i].rnw)
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i3c_xfers[i].len = RESP_DATA_LENGTH(xfer[i].response);
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@@ -383,15 +394,11 @@ static int i3c_hci_i2c_xfers(struct i2c_dev_desc *dev,
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last = i - 1;
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xfer[last].cmd_desc[0] |= CMD_0_TOC;
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xfer[last].completion = &done;
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xfer[last].timeout = m->i2c.timeout;
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ret = hci->io->queue_xfer(hci, xfer, nxfers);
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ret = i3c_hci_process_xfer(hci, xfer, nxfers);
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if (ret)
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goto out;
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if (!wait_for_completion_timeout(&done, m->i2c.timeout) &&
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hci->io->dequeue_xfer(hci, xfer, nxfers)) {
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ret = -ETIMEDOUT;
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goto out;
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}
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for (i = 0; i < nxfers; i++) {
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if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) {
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ret = -EIO;
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@@ -89,6 +89,7 @@ struct hci_xfer {
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unsigned int data_len;
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unsigned int cmd_tid;
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struct completion *completion;
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unsigned long timeout;
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union {
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struct {
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/* PIO specific */
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@@ -156,5 +157,6 @@ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
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void amd_set_od_pp_timing(struct i3c_hci *hci);
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void amd_set_resp_buf_thld(struct i3c_hci *hci);
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void i3c_hci_sync_irq_inactive(struct i3c_hci *hci);
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int i3c_hci_process_xfer(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
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#endif
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