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drm/amd/display: Remove legacy comments
To improve the code readability, this commit removes a set of commented and not used functions for a long time. Notice that now we have the amdgpu_dm_dtn_log, which prints all the relevant information that we need. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira
committed by
Alex Deucher
Alex Deucher
parent
2334470369
commit
7969b6ecb3
@@ -2199,129 +2199,6 @@ void dcn10_enable_per_frame_crtc_position_reset(
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DC_SYNC_INFO("Multi-display sync is complete\n");
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}
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/*static void print_rq_dlg_ttu(
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struct dc *dc,
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struct pipe_ctx *pipe_ctx)
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{
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DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
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"\n============== DML TTU Output parameters [%d] ==============\n"
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"qos_level_low_wm: %d, \n"
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"qos_level_high_wm: %d, \n"
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"min_ttu_vblank: %d, \n"
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"qos_level_flip: %d, \n"
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"refcyc_per_req_delivery_l: %d, \n"
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"qos_level_fixed_l: %d, \n"
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"qos_ramp_disable_l: %d, \n"
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"refcyc_per_req_delivery_pre_l: %d, \n"
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"refcyc_per_req_delivery_c: %d, \n"
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"qos_level_fixed_c: %d, \n"
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"qos_ramp_disable_c: %d, \n"
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"refcyc_per_req_delivery_pre_c: %d\n"
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"=============================================================\n",
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pipe_ctx->pipe_idx,
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pipe_ctx->ttu_regs.qos_level_low_wm,
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pipe_ctx->ttu_regs.qos_level_high_wm,
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pipe_ctx->ttu_regs.min_ttu_vblank,
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pipe_ctx->ttu_regs.qos_level_flip,
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pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
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pipe_ctx->ttu_regs.qos_level_fixed_l,
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pipe_ctx->ttu_regs.qos_ramp_disable_l,
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pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
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pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
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pipe_ctx->ttu_regs.qos_level_fixed_c,
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pipe_ctx->ttu_regs.qos_ramp_disable_c,
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pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
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);
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DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
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"\n============== DML DLG Output parameters [%d] ==============\n"
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"refcyc_h_blank_end: %d, \n"
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"dlg_vblank_end: %d, \n"
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"min_dst_y_next_start: %d, \n"
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"refcyc_per_htotal: %d, \n"
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"refcyc_x_after_scaler: %d, \n"
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"dst_y_after_scaler: %d, \n"
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"dst_y_prefetch: %d, \n"
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"dst_y_per_vm_vblank: %d, \n"
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"dst_y_per_row_vblank: %d, \n"
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"ref_freq_to_pix_freq: %d, \n"
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"vratio_prefetch: %d, \n"
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"refcyc_per_pte_group_vblank_l: %d, \n"
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"refcyc_per_meta_chunk_vblank_l: %d, \n"
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"dst_y_per_pte_row_nom_l: %d, \n"
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"refcyc_per_pte_group_nom_l: %d, \n",
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pipe_ctx->pipe_idx,
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pipe_ctx->dlg_regs.refcyc_h_blank_end,
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pipe_ctx->dlg_regs.dlg_vblank_end,
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pipe_ctx->dlg_regs.min_dst_y_next_start,
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pipe_ctx->dlg_regs.refcyc_per_htotal,
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pipe_ctx->dlg_regs.refcyc_x_after_scaler,
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pipe_ctx->dlg_regs.dst_y_after_scaler,
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pipe_ctx->dlg_regs.dst_y_prefetch,
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pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
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pipe_ctx->dlg_regs.dst_y_per_row_vblank,
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pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
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pipe_ctx->dlg_regs.vratio_prefetch,
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pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
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pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
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pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
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pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
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);
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DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
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"\ndst_y_per_meta_row_nom_l: %d, \n"
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"refcyc_per_meta_chunk_nom_l: %d, \n"
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"refcyc_per_line_delivery_pre_l: %d, \n"
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"refcyc_per_line_delivery_l: %d, \n"
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"vratio_prefetch_c: %d, \n"
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"refcyc_per_pte_group_vblank_c: %d, \n"
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"refcyc_per_meta_chunk_vblank_c: %d, \n"
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"dst_y_per_pte_row_nom_c: %d, \n"
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"refcyc_per_pte_group_nom_c: %d, \n"
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"dst_y_per_meta_row_nom_c: %d, \n"
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"refcyc_per_meta_chunk_nom_c: %d, \n"
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"refcyc_per_line_delivery_pre_c: %d, \n"
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"refcyc_per_line_delivery_c: %d \n"
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"========================================================\n",
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pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
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pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
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pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
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pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
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pipe_ctx->dlg_regs.vratio_prefetch_c,
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pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
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pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
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pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
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pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
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pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
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pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
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pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
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pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
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);
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DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
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"\n============== DML RQ Output parameters [%d] ==============\n"
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"chunk_size: %d \n"
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"min_chunk_size: %d \n"
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"meta_chunk_size: %d \n"
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"min_meta_chunk_size: %d \n"
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"dpte_group_size: %d \n"
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"mpte_group_size: %d \n"
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"swath_height: %d \n"
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"pte_row_height_linear: %d \n"
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"========================================================\n",
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pipe_ctx->pipe_idx,
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pipe_ctx->rq_regs.rq_regs_l.chunk_size,
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pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
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pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
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pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
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pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
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pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
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pipe_ctx->rq_regs.rq_regs_l.swath_height,
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pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
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);
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}
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*/
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static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
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struct vm_system_aperture_param *apt,
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struct dce_hwseq *hws)
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@@ -2429,43 +2306,6 @@ static void dcn10_enable_plane(
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pipe_ctx->stream_res.opp,
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true);
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/* TODO: enable/disable in dm as per update type.
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if (plane_state) {
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DC_LOG_DC(dc->ctx->logger,
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"Pipe:%d 0x%x: addr hi:0x%x, "
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"addr low:0x%x, "
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"src: %d, %d, %d,"
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" %d; dst: %d, %d, %d, %d;\n",
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pipe_ctx->pipe_idx,
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plane_state,
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plane_state->address.grph.addr.high_part,
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plane_state->address.grph.addr.low_part,
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plane_state->src_rect.x,
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plane_state->src_rect.y,
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plane_state->src_rect.width,
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plane_state->src_rect.height,
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plane_state->dst_rect.x,
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plane_state->dst_rect.y,
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plane_state->dst_rect.width,
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plane_state->dst_rect.height);
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DC_LOG_DC(dc->ctx->logger,
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"Pipe %d: width, height, x, y format:%d\n"
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"viewport:%d, %d, %d, %d\n"
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"recout: %d, %d, %d, %d\n",
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pipe_ctx->pipe_idx,
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plane_state->format,
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pipe_ctx->plane_res.scl_data.viewport.width,
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pipe_ctx->plane_res.scl_data.viewport.height,
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pipe_ctx->plane_res.scl_data.viewport.x,
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pipe_ctx->plane_res.scl_data.viewport.y,
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pipe_ctx->plane_res.scl_data.recout.width,
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pipe_ctx->plane_res.scl_data.recout.height,
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pipe_ctx->plane_res.scl_data.recout.x,
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pipe_ctx->plane_res.scl_data.recout.y);
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print_rq_dlg_ttu(dc, pipe_ctx);
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}
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*/
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if (dc->config.gpu_vm_support)
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dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
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