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drm/msm/dpu: rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg

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Rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg and move it
to dpu_hw_utils file so that other modules in addition to
SSPP such as writeback can use it as all the fields can
be used by writeback as well.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/483503/
Link: https://lore.kernel.org/r/1650984096-9964-6-git-send-email-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Abhinav Kumar
2022-04-26 07:41:22 -07:00
committed by Dmitry Baryshkov
parent e1a950eec2
commit 786de937c4
4 changed files with 19 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
View File

@@ -627,7 +627,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
}
static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
struct dpu_hw_pipe_cdp_cfg *cfg,
struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index)
{
u32 idx;

18
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
View File

@@ -192,22 +192,6 @@ enum {
DPU_SSPP_CDP_PRELOAD_AHEAD_64
};
/**
* struct dpu_hw_pipe_cdp_cfg : CDP configuration
* @enable: true to enable CDP
* @ubwc_meta_enable: true to enable ubwc metadata preload
* @tile_amortize_enable: true to enable amortization control for tile format
* @preload_ahead: number of request to preload ahead
* DPU_SSPP_CDP_PRELOAD_AHEAD_32,
* DPU_SSPP_CDP_PRELOAD_AHEAD_64
*/
struct dpu_hw_pipe_cdp_cfg {
bool enable;
bool ubwc_meta_enable;
bool tile_amortize_enable;
u32 preload_ahead;
};
/**
* struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
* @size: size to prefill in bytes, or zero to disable
@@ -359,7 +343,7 @@ struct dpu_hw_sspp_ops {
* @index: rectangle index in multirect
*/
void (*setup_cdp)(struct dpu_hw_pipe *ctx,
struct dpu_hw_pipe_cdp_cfg *cfg,
struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index);
};

15
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
View File

@@ -298,6 +298,21 @@ struct dpu_drm_scaler_v2 {
struct dpu_drm_de_v1 de;
};
/**
* struct dpu_hw_cdp_cfg : CDP configuration
* @enable: true to enable CDP
* @ubwc_meta_enable: true to enable ubwc metadata preload
* @tile_amortize_enable: true to enable amortization control for tile format
* @preload_ahead: number of request to preload ahead
* DPU_*_CDP_PRELOAD_AHEAD_32,
* DPU_*_CDP_PRELOAD_AHEAD_64
*/
struct dpu_hw_cdp_cfg {
bool enable;
bool ubwc_meta_enable;
bool tile_amortize_enable;
u32 preload_ahead;
};
u32 *dpu_hw_util_get_log_mask_ptr(void);

4
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View File

@@ -1246,9 +1246,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pstate->multirect_index);
if (pdpu->pipe_hw->ops.setup_cdp) {
struct dpu_hw_pipe_cdp_cfg cdp_cfg;
struct dpu_hw_cdp_cfg cdp_cfg;
memset(&cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
[DPU_PERF_CDP_USAGE_RT].rd_enable;