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drm/amd/display: Update pmfw_driver_if new structure
[why] pmfw header file updated, need align with data structure. [How] Update the data structure. Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu
committed by
Alex Deucher
Alex Deucher
parent
43693e859b
commit
776ecb46ff
@@ -507,7 +507,7 @@ static struct wm_table lpddr5_wm_table = {
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}
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};
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static DpmClocks_t dummy_clocks;
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static DpmClocks_t_dcn35 dummy_clocks;
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static struct dcn35_watermarks dummy_wms = { 0 };
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@@ -597,7 +597,7 @@ static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
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static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
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struct dcn35_smu_dpm_clks *smu_dpm_clks)
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{
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DpmClocks_t *table = smu_dpm_clks->dpm_clks;
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DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
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if (!clk_mgr->smu_ver)
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return;
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@@ -627,88 +627,158 @@ static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
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return max;
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}
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static unsigned int find_clk_for_voltage(
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const DpmClocks_t *clock_table,
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const uint32_t clocks[],
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unsigned int voltage)
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static inline bool is_valid_clock_value(uint32_t clock_value)
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{
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int i;
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int max_voltage = 0;
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int clock = 0;
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return clock_value > 1 && clock_value < 100000;
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}
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for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
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if (clock_table->SocVoltage[i] == voltage) {
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return clocks[i];
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} else if (clock_table->SocVoltage[i] >= max_voltage &&
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clock_table->SocVoltage[i] < voltage) {
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max_voltage = clock_table->SocVoltage[i];
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clock = clocks[i];
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}
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static unsigned int convert_wck_ratio(uint8_t wck_ratio)
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{
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switch (wck_ratio) {
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case WCK_RATIO_1_2:
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return 2;
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case WCK_RATIO_1_4:
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return 4;
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/* Find lowest DPM, FCLK is filled in reverse order*/
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default:
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break;
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}
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ASSERT(clock);
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return clock;
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return 1;
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}
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static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
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struct integrated_info *bios_info,
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const DpmClocks_t *clock_table)
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DpmClocks_t_dcn35 *clock_table)
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{
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int i, j;
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struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
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uint32_t max_dispclk = 0, max_dppclk = 0;
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struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
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uint32_t max_pstate = 0, max_uclk = 0, max_fclk = 0;
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uint32_t min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
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int i;
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j = -1;
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ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
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/* Find lowest DPM, FCLK is filled in reverse order*/
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for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
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if (clock_table->DfPstateTable[i].FClk != 0) {
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j = i;
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break;
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for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
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if (is_valid_clock_value(clock_table->MemPstateTable[i].UClk) &&
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clock_table->MemPstateTable[i].UClk > max_uclk) {
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max_uclk = clock_table->MemPstateTable[i].UClk;
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max_pstate = i;
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}
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}
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if (j == -1) {
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/* clock table is all 0s, just use our own hardcode */
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ASSERT(0);
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return;
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}
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/* We expect the table to contain at least one valid Uclk entry. */
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ASSERT(is_valid_clock_value(max_uclk));
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bw_params->clk_table.num_entries = j + 1;
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/* dispclk and dppclk can be max at any voltage, same number of levels for both */
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if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
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clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
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max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
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max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
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max_dispclk = find_max_clk_value(clock_table->DispClocks,
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clock_table->NumDispClkLevelsEnabled);
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max_dppclk = find_max_clk_value(clock_table->DppClocks,
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clock_table->NumDispClkLevelsEnabled);
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} else {
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ASSERT(0);
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}
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if (clock_table->NumFclkLevelsEnabled <= NUM_FCLK_DPM_LEVELS)
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max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq,
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clock_table->NumFclkLevelsEnabled);
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for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
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bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
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bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
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bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
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switch (clock_table->DfPstateTable[j].WckRatio) {
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case WCK_RATIO_1_2:
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bw_params->clk_table.entries[i].wck_ratio = 2;
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break;
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case WCK_RATIO_1_4:
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bw_params->clk_table.entries[i].wck_ratio = 4;
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break;
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default:
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bw_params->clk_table.entries[i].wck_ratio = 1;
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for (i = 0; i < clock_table->NumMemPstatesEnabled; i++) {
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uint32_t min_uclk = clock_table->MemPstateTable[0].UClk;
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int j;
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for (j = 1; j < clock_table->NumMemPstatesEnabled; j++) {
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if (is_valid_clock_value(clock_table->MemPstateTable[j].UClk) &&
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clock_table->MemPstateTable[j].UClk < min_uclk &&
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clock_table->MemPstateTable[j].Voltage <= clock_table->SocVoltage[i]) {
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min_uclk = clock_table->MemPstateTable[j].UClk;
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min_pstate = j;
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}
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}
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bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
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bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
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for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
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if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
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break;
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bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
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bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
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bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
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bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
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bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
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bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
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bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
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bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
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bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
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bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
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}
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bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
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clock_table->MemPstateTable[min_pstate].WckRatio);
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}
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/* Make sure to include at least one entry at highest pstate */
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if (max_pstate != min_pstate || i == 0) {
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if (i > MAX_NUM_DPM_LVL - 1)
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i = MAX_NUM_DPM_LVL - 1;
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bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
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bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
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bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
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bw_params->clk_table.entries[i].dcfclk_mhz =
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find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
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bw_params->clk_table.entries[i].socclk_mhz =
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find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
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bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
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bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
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bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
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clock_table->MemPstateTable[max_pstate].WckRatio);
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i++;
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}
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bw_params->clk_table.num_entries = i--;
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bw_params->clk_table.entries[i].socclk_mhz =
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find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
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bw_params->clk_table.entries[i].dispclk_mhz =
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find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
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bw_params->clk_table.entries[i].dppclk_mhz =
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find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
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bw_params->clk_table.entries[i].fclk_mhz =
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find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
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ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
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bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
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bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
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bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
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bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
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bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
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bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
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bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
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bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
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bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
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for (i = 0; i < bw_params->clk_table.num_entries; i++) {
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if (!bw_params->clk_table.entries[i].fclk_mhz) {
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bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
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bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
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bw_params->clk_table.entries[i].voltage = def_max.voltage;
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}
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if (!bw_params->clk_table.entries[i].dcfclk_mhz)
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bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
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if (!bw_params->clk_table.entries[i].socclk_mhz)
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bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
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if (!bw_params->clk_table.entries[i].dispclk_mhz)
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bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
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if (!bw_params->clk_table.entries[i].dppclk_mhz)
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bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
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if (!bw_params->clk_table.entries[i].fclk_mhz)
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bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
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if (!bw_params->clk_table.entries[i].phyclk_mhz)
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bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
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if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
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bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
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if (!bw_params->clk_table.entries[i].dtbclk_mhz)
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bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
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}
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ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
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bw_params->vram_type = bios_info->memory_type;
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bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
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bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
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for (i = 0; i < WM_SET_COUNT; i++) {
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@@ -938,10 +1008,10 @@ void dcn35_clk_mgr_construct(
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}
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ASSERT(clk_mgr->smu_wm_set.wm_set);
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smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
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smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
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clk_mgr->base.base.ctx,
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DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
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sizeof(DpmClocks_t),
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sizeof(DpmClocks_t_dcn35),
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&smu_dpm_clks.mc_address.quad_part);
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if (smu_dpm_clks.dpm_clks == NULL) {
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@@ -988,14 +1058,16 @@ void dcn35_clk_mgr_construct(
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"NumDispClkLevelsEnabled: %d\n"
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"NumSocClkLevelsEnabled: %d\n"
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"VcnClkLevelsEnabled: %d\n"
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"NumDfPst atesEnabled: %d\n"
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"FClkLevelsEnabled: %d\n"
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"NumMemPstatesEnabled: %d\n"
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"MinGfxClk: %d\n"
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"MaxGfxClk: %d\n",
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smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
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smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
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smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
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smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
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smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
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smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
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smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
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smu_dpm_clks.dpm_clks->MinGfxClk,
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smu_dpm_clks.dpm_clks->MaxGfxClk);
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for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
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@@ -1011,17 +1083,23 @@ void dcn35_clk_mgr_construct(
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DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
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i, smu_dpm_clks.dpm_clks->SocClocks[i]);
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}
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for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
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for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
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DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
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i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
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DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
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i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
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}
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for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
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DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
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i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
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for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
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DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
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"smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
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"smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
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i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
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i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
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i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
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for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
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DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
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"smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
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"smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
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i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
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i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
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i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
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}
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if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
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@@ -79,7 +79,9 @@ typedef struct {
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#define NUM_SOCCLK_DPM_LEVELS 8
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#define NUM_VCN_DPM_LEVELS 8
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#define NUM_SOC_VOLTAGE_LEVELS 8
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#define NUM_DF_PSTATE_LEVELS 4
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#define NUM_VPE_DPM_LEVELS 8
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#define NUM_FCLK_DPM_LEVELS 8
|
||||
#define NUM_MEM_PSTATE_LEVELS 4
|
||||
|
||||
typedef enum{
|
||||
WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1;
|
||||
@@ -89,12 +91,12 @@ typedef enum{
|
||||
} WCK_RATIO_e;
|
||||
|
||||
typedef struct {
|
||||
uint32_t FClk;
|
||||
uint32_t UClk;
|
||||
uint32_t MemClk;
|
||||
uint32_t Voltage;
|
||||
uint8_t WckRatio;
|
||||
uint8_t Spare[3];
|
||||
} DfPstateTable_t;
|
||||
} MemPstateTable_t;
|
||||
|
||||
//Freq in MHz
|
||||
//Voltage in milli volts with 2 fractional bits
|
||||
@@ -105,19 +107,37 @@ typedef struct {
|
||||
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
|
||||
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];
|
||||
uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
|
||||
uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
|
||||
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
|
||||
DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
|
||||
MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];
|
||||
|
||||
uint8_t NumDcfClkLevelsEnabled;
|
||||
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
|
||||
uint8_t NumSocClkLevelsEnabled;
|
||||
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
|
||||
uint8_t NumDfPstatesEnabled;
|
||||
uint8_t spare[3];
|
||||
uint8_t VpeClkLevelsEnabled;
|
||||
uint8_t NumMemPstatesEnabled;
|
||||
uint8_t NumFclkLevelsEnabled;
|
||||
uint8_t spare[2];
|
||||
|
||||
uint32_t MinGfxClk;
|
||||
uint32_t MaxGfxClk;
|
||||
} DpmClocks_t;
|
||||
} DpmClocks_t_dcn35;
|
||||
|
||||
|
||||
// Throttler Status Bitmask
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define TABLE_BIOS_IF 0 // Called by BIOS
|
||||
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
|
||||
@@ -139,7 +159,7 @@ struct dcn35_watermarks {
|
||||
};
|
||||
|
||||
struct dcn35_smu_dpm_clks {
|
||||
DpmClocks_t *dpm_clks;
|
||||
DpmClocks_t_dcn35 *dpm_clks;
|
||||
union large_integer mc_address;
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user