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net: dsa: microchip: Use regs[] to access REG_PTP_RTC_SEC
Accesses to the PTP_RTC_SEC register are done through a hardcoded address which doesn't match with the KSZ8463's register layout. Add a new entry for the PTP_RTC_SEC register in the regs[] tables. Use the regs[] table to retrieve the PTP_RTC_SEC register address when accessing it. Remove the macro defining the address to prevent further use. Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com> Link: https://patch.msgid.link/20260105-ksz-rework-v1-5-a68df7f57375@bootlin.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
committed by
Paolo Abeni
parent
0ee0566fc2
commit
776ad30de0
@@ -571,6 +571,7 @@ static const u16 ksz8463_regs[] = {
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[S_MULTICAST_CTRL] = 0x04,
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[PTP_CLK_CTRL] = 0x0600,
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[PTP_RTC_NANOSEC] = 0x0604,
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[PTP_RTC_SEC] = 0x0608,
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};
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static const u32 ksz8463_masks[] = {
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@@ -807,6 +808,7 @@ static const u16 ksz9477_regs[] = {
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[REG_PORT_PME_CTRL] = 0x0017,
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[PTP_CLK_CTRL] = 0x0500,
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[PTP_RTC_NANOSEC] = 0x0504,
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[PTP_RTC_SEC] = 0x0508,
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};
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static const u32 ksz9477_masks[] = {
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@@ -273,6 +273,7 @@ enum ksz_regs {
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REG_PORT_PME_CTRL,
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PTP_CLK_CTRL,
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PTP_RTC_NANOSEC,
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PTP_RTC_SEC,
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};
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enum ksz_masks {
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@@ -604,7 +604,7 @@ static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts)
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if (ret)
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return ret;
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ret = ksz_read32(dev, REG_PTP_RTC_SEC, &seconds);
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ret = ksz_read32(dev, regs[PTP_RTC_SEC], &seconds);
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if (ret)
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return ret;
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@@ -691,7 +691,7 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp,
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if (ret)
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goto unlock;
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ret = ksz_write32(dev, REG_PTP_RTC_SEC, ts->tv_sec);
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ret = ksz_write32(dev, regs[PTP_RTC_SEC], ts->tv_sec);
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if (ret)
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goto unlock;
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@@ -782,7 +782,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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if (ret)
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goto unlock;
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ret = ksz_write32(dev, REG_PTP_RTC_SEC, abs(sec));
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ret = ksz_write32(dev, regs[PTP_RTC_SEC], abs(sec));
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if (ret)
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goto unlock;
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@@ -29,8 +29,6 @@
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#define PTP_RTC_SUB_NANOSEC_M 0x0007
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#define PTP_RTC_0NS 0x00
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#define REG_PTP_RTC_SEC 0x0508
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#define REG_PTP_SUBNANOSEC_RATE 0x050C
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#define PTP_SUBNANOSEC_M 0x3FFFFFFF
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