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media: verisilicon: Enable NV15 support for Rockchip VDPU981
This is a "customer" format, though on Rockchip RK3588 it has been verified to be NV15 format, which matches what the GPU and display handles has 10bit pixel formats. Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
committed by
Hans Verkuil
parent
d52b9b7e2f
commit
7713800a6c
@@ -77,6 +77,7 @@ int hantro_get_format_depth(u32 fourcc)
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switch (fourcc) {
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case V4L2_PIX_FMT_P010:
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case V4L2_PIX_FMT_P010_4L4:
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case V4L2_PIX_FMT_NV15:
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case V4L2_PIX_FMT_NV15_4L4:
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return 10;
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default:
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@@ -2202,6 +2202,10 @@ static void rockchip_vpu981_postproc_enable(struct hantro_ctx *ctx)
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case V4L2_PIX_FMT_NV12:
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hantro_reg_write(vpu, &av1_pp_out_format, 3);
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break;
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case V4L2_PIX_FMT_NV15:
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/* this mapping is RK specific */
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hantro_reg_write(vpu, &av1_pp_out_format, 10);
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break;
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default:
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hantro_reg_write(vpu, &av1_pp_out_format, 0);
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}
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@@ -92,6 +92,20 @@ static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_NV15,
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.codec_mode = HANTRO_MODE_NONE,
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.match_depth = true,
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.postprocessed = true,
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.frmsize = {
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.min_width = ROCKCHIP_VPU981_MIN_SIZE,
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.max_width = FMT_4K_WIDTH,
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.step_width = MB_DIM,
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.min_height = ROCKCHIP_VPU981_MIN_SIZE,
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.max_height = FMT_4K_HEIGHT,
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.step_height = MB_DIM,
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},
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},
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{
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.fourcc = V4L2_PIX_FMT_P010,
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.codec_mode = HANTRO_MODE_NONE,
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