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arm64: dts: qcom: sm8250: add wsa and va codec macros
Add support for WSA and VA codec macros along with WSA soundwire controller required for getting audio on RB5. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20201202180741.16386-5-srinivas.kandagatla@linaro.org [bjorn: Replaced LPASS_CDC clock defines with constants] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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committed by
Bjorn Andersson
parent
3160c1b894
commit
768270ca57
@@ -1264,6 +1264,47 @@ tcsr_mutex: hwlock@1f40000 {
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#hwlock-cells = <1>;
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};
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wsamacro: codec@3240000 {
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compatible = "qcom,sm8250-lpass-wsa-macro";
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reg = <0 0x03240000 0 0x1000>;
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clocks = <&audiocc 1>,
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<&audiocc 0>,
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<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&aoncc 0>,
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<&vamacro>;
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clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
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#clock-cells = <0>;
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clock-frequency = <9600000>;
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clock-output-names = "mclk";
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#sound-dai-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&wsa_swr_active>;
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};
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swr0: soundwire-controller@3250000 {
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reg = <0 0x03250000 0 0x2000>;
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compatible = "qcom,soundwire-v1.5.1";
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&wsamacro>;
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clock-names = "iface";
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qcom,din-ports = <2>;
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qcom,dout-ports = <6>;
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qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
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qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
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qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
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qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
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#sound-dai-cells = <1>;
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#address-cells = <2>;
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#size-cells = <0>;
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};
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audiocc: clock-controller@3300000 {
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compatible = "qcom,sm8250-lpass-audiocc";
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reg = <0 0x03300000 0 0x30000>;
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@@ -1274,6 +1315,21 @@ audiocc: clock-controller@3300000 {
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clock-names = "core", "audio", "bus";
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};
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vamacro: codec@3370000 {
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compatible = "qcom,sm8250-lpass-va-macro";
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reg = <0 0x03370000 0 0x1000>;
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clocks = <&aoncc 0>,
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<&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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clock-names = "mclk", "macro", "dcodec";
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#clock-cells = <0>;
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clock-frequency = <9600000>;
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clock-output-names = "fsgen";
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#sound-dai-cells = <1>;
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};
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aoncc: clock-controller@3380000 {
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compatible = "qcom,sm8250-lpass-aoncc";
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reg = <0 0x03380000 0 0x40000>;
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