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drm/amd/pm: re-enable MC access after PrepareMp1ForUnload on SMU V15 APUs

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During smu_v15_0_0_system_features_control(), the driver sends a
PrepareMp1ForUnload message to PMFW. PMFW then performs nBIF and SYSHUB
function-level resets (FLR), disabling PCIe CFG space reset, which
clears the framebuffer enable bit to zero and disables MC (memory controller)
access from the host.

Re-enable MC access via the nbio mc_access_enable callback right after
PrepareMp1ForUnload completes in smu_v15_0_0_system_features_control().

Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com>
Signed-off-by: Suresh Guttula <Suresh.Guttula@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 840a3c5aeae779a3bc75d7f747c3ed18b1af6507)
Cc: stable@vger.kernel.org
This commit is contained in:
Shubhankar Milind Sardeshpande
2026-05-21 10:55:18 +05:30
committed by Alex Deucher
parent 1c2d7a6566
commit 76589bcc73
1 changed files with 6 additions and 1 deletions
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7
drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c
View File

@@ -227,9 +227,14 @@ static int smu_v15_0_0_system_features_control(struct smu_context *smu, bool en)
struct amdgpu_device *adev = smu->adev;
int ret = 0;
if (!en && !adev->in_s0ix)
if (!en && !adev->in_s0ix) {
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
/* SMU resets BIF_FB_EN to zero, re-enable MC access on APUs with SMU V15 */
if (!ret && adev->nbio.funcs && adev->nbio.funcs->mc_access_enable)
adev->nbio.funcs->mc_access_enable(adev, true);
}
return ret;
}