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drm/amd/display: Formula refactor for calculating DPP CLK DTO

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[Why]
Previous formula for calculating DPP CLK DTO was
hard to understand.

[How]
Replace with easier to understand formula that produces
same results.

Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sung Lee
2019-12-05 11:58:20 -05:00
committed by Alex Deucher
parent 5479034576
commit 760ef473f2
1 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
View File

@@ -50,20 +50,20 @@ void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
if (dccg->ref_dppclk && req_dppclk) {
int ref_dppclk = dccg->ref_dppclk;
int modulo, phase;
ASSERT(req_dppclk <= ref_dppclk);
/* need to clamp to 8 bits */
if (ref_dppclk > 0xff) {
int divider = (ref_dppclk + 0xfe) / 0xff;
// phase / modulo = dpp pipe clk / dpp global clk
modulo = 0xff; // use FF at the end
phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
ref_dppclk /= divider;
req_dppclk = (req_dppclk + divider - 1) / divider;
if (req_dppclk > ref_dppclk)
req_dppclk = ref_dppclk;
if (phase > 0xff) {
ASSERT(false);
phase = 0xff;
}
REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
DPPCLK0_DTO_PHASE, req_dppclk,
DPPCLK0_DTO_MODULO, ref_dppclk);
DPPCLK0_DTO_PHASE, phase,
DPPCLK0_DTO_MODULO, modulo);
REG_UPDATE(DPPCLK_DTO_CTRL,
DPPCLK_DTO_ENABLE[dpp_inst], 1);
} else {