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synced 2026-05-01 01:14:19 -04:00
drm/amd/display: Not reset front end when program back end.
Since front end is programmed before back end programming, no need to reset front end in back end programming. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
7a5086a71e
commit
74707de336
@@ -850,6 +850,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
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if (!dcb->funcs->is_accelerated_mode(dcb))
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dc->hwss.enable_accelerated_mode(dc);
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for (i = 0; i < context->stream_count; i++) {
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const struct dc_sink *sink = context->streams[i]->sink;
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@@ -928,7 +930,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
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return (result == DC_OK);
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}
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bool dc_post_update_surfaces_to_stream(struct dc *dc)
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{
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int i;
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@@ -617,32 +617,6 @@ static void plane_atomic_disable(struct dc *dc,
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verify_allow_pstate_change_high(dc->hwseq);
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}
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/*
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* kill power to plane hw
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* note: cannot power down until plane is disable
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*/
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static void plane_atomic_power_down(struct dc *dc, int fe_idx)
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{
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struct dce_hwseq *hws = dc->hwseq;
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struct dpp *dpp = dc->res_pool->dpps[fe_idx];
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if (REG(DC_IP_REQUEST_CNTL)) {
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REG_SET(DC_IP_REQUEST_CNTL, 0,
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IP_REQUEST_EN, 1);
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dpp_pg_control(hws, fe_idx, false);
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hubp_pg_control(hws, fe_idx, false);
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dpp->funcs->dpp_reset(dpp);
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REG_SET(DC_IP_REQUEST_CNTL, 0,
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IP_REQUEST_EN, 0);
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dm_logger_write(dc->ctx->logger, LOG_DEBUG,
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"Power gated front end %d\n", fe_idx);
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if (dc->debug.sanity_checks)
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verify_allow_pstate_change_high(dc->hwseq);
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}
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}
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static void reset_front_end(
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struct dc *dc,
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int fe_idx)
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@@ -792,56 +766,6 @@ static void reset_hw_ctx_wrap(
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{
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int i;
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/* Reset Front End*/
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/* Lock*/
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
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struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
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if (cur_pipe_ctx->stream)
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tg->funcs->lock(tg);
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}
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/* Disconnect*/
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for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
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struct pipe_ctx *pipe_ctx_old =
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&dc->current_state->res_ctx.pipe_ctx[i];
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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if (!pipe_ctx->stream ||
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!pipe_ctx->plane_state ||
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pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
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plane_atomic_disconnect(dc, i);
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}
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}
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/* Unlock*/
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for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
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struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
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struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
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if (cur_pipe_ctx->stream)
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tg->funcs->unlock(tg);
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}
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/* Disable and Powerdown*/
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for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
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struct pipe_ctx *pipe_ctx_old =
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&dc->current_state->res_ctx.pipe_ctx[i];
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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/*if (!pipe_ctx_old->stream)
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continue;*/
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if (pipe_ctx->stream && pipe_ctx->plane_state
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&& !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
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continue;
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plane_atomic_disable(dc, i);
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if (!pipe_ctx->stream || !pipe_ctx->plane_state)
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plane_atomic_power_down(dc, i);
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}
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/* Reset Back End*/
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for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
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struct pipe_ctx *pipe_ctx_old =
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