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drm/amdgpu: Keep SDMAv4.4.2 active during reset

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During ASIC wide reset, SDMA shouldn't be clockgated and be ready to
accept freeze requests from PMFW. For that, don't stop SDMA engine
during reset and keep the clocks active.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lijo Lazar
2023-01-17 16:54:49 +05:30
committed by Alex Deucher
parent b2ef2fdffe
commit 7389c75114
1 changed files with 8 additions and 0 deletions
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8
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
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@@ -566,6 +566,11 @@ static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
if (adev->sdma.has_page_queue)
sdma_v4_4_2_inst_page_stop(adev, inst_mask);
/* SDMA FW needs to respond to FREEZE requests during reset.
* Keep it running during reset */
if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
return;
}
for_each_inst(i, inst_mask) {
@@ -1435,6 +1440,9 @@ static int sdma_v4_4_2_suspend(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (amdgpu_in_reset(adev))
sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
return sdma_v4_4_2_hw_fini(adev);
}