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drm/amd/display: handle max_vstartup larger than vblank_end

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When vstartup is larger than vblank end we need to set v_fp2
to allow for this early start

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
2018-09-14 15:32:33 -04:00
committed by Alex Deucher
parent 09dea6bfb1
commit 72942b3de8
1 changed files with 5 additions and 6 deletions
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11
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
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@@ -274,10 +274,12 @@ void optc1_program_timing(
* program the reg for interrupt postition.
*/
vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
if (vertical_line_start < 0) {
ASSERT(0);
v_fp2 = 0;
if (vertical_line_start < 0)
v_fp2 = -vertical_line_start;
if (vertical_line_start < 0)
vertical_line_start = 0;
}
REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start);
@@ -296,9 +298,6 @@ void optc1_program_timing(
if (patched_crtc_timing.flags.INTERLACE == 1)
field_num = 1;
}
v_fp2 = 0;
if (optc->dlg_otg_param.vstartup_start > asic_blank_end)
v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end;
/* Interlace */
if (patched_crtc_timing.flags.INTERLACE == 1) {