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iommu/arm-smmu-qcom: Make set_stall work when the device is on

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Up until now we have only called the set_stall callback during
initialization when the device is off. But we will soon start calling it
to temporarily disable stall-on-fault when the device is on, so handle
that by checking if the device is on and writing SCTLR.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Link: https://lore.kernel.org/r/20250520-msm-gpu-fault-fixes-next-v8-3-fce6ee218787@gmail.com
[will: Fix "mixed declarations and code" warning from sparse]
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Connor Abbott
2025-05-20 15:08:56 -04:00
committed by Will Deacon
parent 3053a2c508
commit 70892277ca
2 changed files with 33 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
View File

@@ -112,12 +112,39 @@ static void qcom_adreno_smmu_set_stall(const void *cookie, bool enabled)
{
struct arm_smmu_domain *smmu_domain = (void *)cookie;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu);
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
u32 mask = BIT(cfg->cbndx);
bool stall_changed = !!(qsmmu->stall_enabled & mask) != enabled;
unsigned long flags;
if (enabled)
qsmmu->stall_enabled |= BIT(cfg->cbndx);
qsmmu->stall_enabled |= mask;
else
qsmmu->stall_enabled &= ~BIT(cfg->cbndx);
qsmmu->stall_enabled &= ~mask;
/*
* If the device is on and we changed the setting, update the register.
* The spec pseudocode says that CFCFG is resampled after a fault, and
* we believe that no implementations cache it in the TLB, so it should
* be safe to change it without a TLB invalidation.
*/
if (stall_changed && pm_runtime_get_if_active(smmu->dev) > 0) {
u32 reg;
spin_lock_irqsave(&smmu_domain->cb_lock, flags);
reg = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR);
if (enabled)
reg |= ARM_SMMU_SCTLR_CFCFG;
else
reg &= ~ARM_SMMU_SCTLR_CFCFG;
arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_SCTLR, reg);
spin_unlock_irqrestore(&smmu_domain->cb_lock, flags);
pm_runtime_put_autosuspend(smmu->dev);
}
}
static void qcom_adreno_smmu_set_prr_bit(const void *cookie, bool set)

6
include/linux/adreno-smmu-priv.h
View File

@@ -45,9 +45,9 @@ struct adreno_smmu_fault_info {
* TTBR0 translation is enabled with the specified cfg
* @get_fault_info: Called by the GPU fault handler to get information about
* the fault
* @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call
* before set_ttbr0_cfg(). If stalling on fault is enabled,
* the GPU driver must call resume_translation()
* @set_stall: Configure whether stall on fault (CFCFG) is enabled. If
* stalling on fault is enabled, the GPU driver must call
* resume_translation()
* @resume_translation: Resume translation after a fault
*
* @set_prr_bit: [optional] Configure the GPU's Partially Resident