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drm/msm/dpu: check for the plane pitch overflow
Check that the plane pitch doesn't overflow the maximum pitch size allowed by the hardware. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/612253/ Link: https://lore.kernel.org/r/20240903-dpu-mode-config-width-v6-13-617e1ecc4b7a@linaro.org
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@@ -12,6 +12,8 @@
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struct dpu_hw_sspp;
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#define DPU_SSPP_MAX_PITCH_SIZE 0xffff
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/**
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* Flags
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*/
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@@ -782,7 +782,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
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{
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struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
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plane);
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int ret = 0, min_scale;
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int i, ret = 0, min_scale;
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struct dpu_plane *pdpu = to_dpu_plane(plane);
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struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
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u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate;
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@@ -856,6 +856,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
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return ret;
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}
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for (i = 0; i < pstate->layout.num_planes; i++)
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if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE)
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return -E2BIG;
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fmt = msm_framebuffer_format(new_plane_state->fb);
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max_linewidth = pdpu->catalog->caps->max_linewidth;
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