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drm/i915/hwmon: Enable PL1 limit when writing limit value to HW

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Previous documentation suggested that the PL1 power limit is always enabled
in HW. However we now find this not to be the case on some platforms (such
as ATSM). Therefore enable the PL1 power limit (by setting the enable bit)
when writing the PL1 limit value to HW.

Bspec: 51864

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230216164944.2366150-3-ashutosh.dixit@intel.com
This commit is contained in:
Ashutosh Dixit
2023-02-16 08:49:44 -08:00
committed by Rodrigo Vivi
parent f99926383b
commit 6fd3d8bf89
1 changed files with 3 additions and 2 deletions
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5
drivers/gpu/drm/i915/i915_hwmon.c
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@@ -385,10 +385,11 @@ hwm_power_max_write(struct hwm_drvdata *ddat, long val)
/* Computation in 64-bits to avoid overflow. Round to nearest. */
nval = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_power, SF_POWER);
nval = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, nval);
hwm_locked_with_pm_intel_uncore_rmw(ddat, hwmon->rg.pkg_rapl_limit,
PKG_PWR_LIM_1,
REG_FIELD_PREP(PKG_PWR_LIM_1, nval));
PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1,
nval);
return 0;
}