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arm64: dts: rockchip: Add I2S rk3588 nodes

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In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM
controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides
another group of four I2S/PCM/TDM controllers.

Add the DT nodes corresponding to the additional controllers.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-5-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Cristian Ciocaltea
2023-04-02 12:50:53 +03:00
committed by Heiko Stuebner
parent 8ae112a555
commit 6f48c6f585
1 changed files with 68 additions and 0 deletions
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68
arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -7,6 +7,74 @@
#include "rk3588-pinctrl.dtsi"
/ {
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 22>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO0>;
resets = <&cru SRST_M_I2S8_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s6_8ch: i2s@fddf4000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf4000 0x0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 4>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S6_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s7_8ch: i2s@fddf8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf8000 0x0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 21>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S7_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s10_8ch: i2s@fde00000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfde00000 0x0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 24>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S10_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
gmac0: ethernet@fe1b0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1b0000 0x0 0x10000>;