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arm64: dts: meson: Add capacity-dmips-mhz attributes to G12B

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Meson G12B SoCs (S922X and A311D) are a big-little design where not all CPUs
are equal; the A53s cores are weaker than the A72s.

Include capacity-dmips-mhz properties to tell the OS there is a difference
in processing capacity. The dmips values are based on similar submissions for
other A53/A72 SoCs: HiSilicon 3660 [1] and Rockchip RK3399 [2].

This change is particularly beneficial for use-cases like retro gaming where
emulators often run on a single core. The OS now chooses an A72 core instead
of an A53 core.

[1] https://lore.kernel.org/patchwork/patch/862742/
[2] https://patchwork.kernel.org/patch/10836577/

Signed-off-by: Frank Hartung <supervisedthinking@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Frank Hartung
2019-09-14 06:49:40 +04:00
committed by Kevin Hilman
parent b255e1268b
commit 6eeaf4d245
1 changed files with 6 additions and 0 deletions
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6
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
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@@ -48,6 +48,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <592>;
next-level-cache = <&l2>;
};
@@ -56,6 +57,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <592>;
next-level-cache = <&l2>;
};
@@ -64,6 +66,7 @@ cpu100: cpu@100 {
compatible = "arm,cortex-a73";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
};
@@ -72,6 +75,7 @@ cpu101: cpu@101 {
compatible = "arm,cortex-a73";
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
};
@@ -80,6 +84,7 @@ cpu102: cpu@102 {
compatible = "arm,cortex-a73";
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
};
@@ -88,6 +93,7 @@ cpu103: cpu@103 {
compatible = "arm,cortex-a73";
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2>;
};