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drm/amd/display: Block subvp if center timing is in use

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[Description]
- FW scheduling algorithm doesn't take into account of it's
  a center timing
- This affects where the subvp mclk switch can be scheduled
  (prevents HUBP vline interrupt from coming in if scheduled
  incorrectly)
- Block subvp center timing cases for now

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee
2022-12-03 14:41:03 -05:00
committed by Alex Deucher
parent 6b81090d6d
commit 6e18c9b35e
3 changed files with 15 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
View File

@@ -112,6 +112,7 @@ bool dcn32_subvp_in_use(struct dc *dc,
bool dcn32_mpo_in_use(struct dc_state *context);
bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);
bool dcn32_is_center_timing(struct pipe_ctx *pipe);
struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
struct dc_state *state,

13
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
View File

@@ -255,6 +255,19 @@ bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)
return false;
}
bool dcn32_is_center_timing(struct pipe_ctx *pipe)
{
bool is_center_timing = false;
if (pipe->stream) {
if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||
pipe->stream->timing.v_addressable != pipe->stream->src.height) {
is_center_timing = true;
}
}
return is_center_timing;
}
/**
* *******************************************************************************************
* dcn32_determine_det_override: Determine DET allocation for each pipe

2
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@@ -691,7 +691,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
* to combine this with SubVP can cause issues with the scheduling).
* - Not TMZ surface
*/
if (pipe->plane_state && !pipe->top_pipe &&
if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&
pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&
vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) {
while (pipe) {