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drm/amd/display: Don't use non-registered VUPDATE on DCE 6

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The VUPDATE interrupt isn't registered on DCE 6, so don't try
to use that.

This fixes a page flip timeout after sleep/resume on DCE 6.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Timur Kristóf
2025-08-25 23:56:31 +02:00
committed by Alex Deucher
parent 043c87d7d5
commit 6cbe6e072c
2 changed files with 23 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@@ -3047,14 +3047,20 @@ static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n",
enable ? "enable" : "disable");
if (enable) {
if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
} else
rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {
if (enable) {
if (amdgpu_dm_crtc_vrr_active(
to_dm_crtc_state(acrtc->base.state)))
rc = amdgpu_dm_crtc_set_vupdate_irq(
&acrtc->base, true);
} else
rc = amdgpu_dm_crtc_set_vupdate_irq(
&acrtc->base, false);
if (rc)
drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
if (rc)
drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n",
enable ? "en" : "dis");
}
irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
/* During gpu-reset we disable and then enable vblank irq, so

16
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
View File

@@ -317,13 +317,17 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
sr_supported && vblank->config.disable_immediate)
drm_crtc_vblank_restore(crtc);
}
/* vblank irq on -> Only need vupdate irq in vrr mode */
if (amdgpu_dm_crtc_vrr_active(acrtc_state))
rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
} else {
/* vblank irq off -> vupdate irq off */
rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
if (dc_supports_vrr(dm->dc->ctx->dce_version)) {
if (enable) {
/* vblank irq on -> Only need vupdate irq in vrr mode */
if (amdgpu_dm_crtc_vrr_active(acrtc_state))
rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
} else {
/* vblank irq off -> vupdate irq off */
rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
}
}
if (rc)