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arm64: dts: ls1028a-rdb: sort nodes alphabetically by label

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In preparation for this board's device tree synchronization with U-Boot,
we must find a common node ordering pattern. Alphabetical sounds about
right.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Vladimir Oltean
2021-12-02 16:15:25 +02:00
committed by Shawn Guo
parent 44d0dfee53
commit 6c5d66cb28
1 changed files with 42 additions and 42 deletions
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84
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
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@@ -102,6 +102,48 @@ can-transceiver {
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&enetc_mdio_pf3 {
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
};
/* VSC8514 QSGMII quad PHY */
qsgmii_phy0: ethernet-phy@10 {
reg = <0x10>;
};
qsgmii_phy1: ethernet-phy@11 {
reg = <0x11>;
};
qsgmii_phy2: ethernet-phy@12 {
reg = <0x12>;
};
qsgmii_phy3: ethernet-phy@13 {
reg = <0x13>;
};
};
&enetc_port0 {
phy-handle = <&sgmii_phy0>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "okay";
};
&enetc_port2 {
status = "okay";
};
&esdhc {
sd-uhs-sdr104;
sd-uhs-sdr50;
@@ -188,48 +230,6 @@ rtc@51 {
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};
&enetc_mdio_pf3 {
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
};
/* VSC8514 QSGMII quad PHY */
qsgmii_phy0: ethernet-phy@10 {
reg = <0x10>;
};
qsgmii_phy1: ethernet-phy@11 {
reg = <0x11>;
};
qsgmii_phy2: ethernet-phy@12 {
reg = <0x12>;
};
qsgmii_phy3: ethernet-phy@13 {
reg = <0x13>;
};
};
&enetc_port0 {
phy-handle = <&sgmii_phy0>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "okay";
};
&enetc_port2 {
status = "okay";
};
&mscc_felix {
status = "okay";
};