mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-11 13:52:02 -04:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: qcom: sdm630: Add clocks and power domains to SMMU nodes

Browse Source 
Add the required clocks and power domains for the SMMUs to work.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210728222542.54269-13-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
AngeloGioacchino Del Regno
2021-07-29 00:25:15 +02:00
committed by Bjorn Andersson
parent a64fa0e23b
commit 6bb717fe56
1 changed files with 28 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@@ -563,9 +563,14 @@ snoc: interconnect@1626000 {
anoc2_smmu: iommu@16c0000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x016c0000 0x40000>;
assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
assigned-clock-rates = <1000>;
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
clock-names = "bus";
#global-interrupts = <2>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
@@ -904,9 +909,22 @@ sd-cd {
kgsl_smmu: iommu@5040000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x05040000 0x10000>;
/*
* GX GDSC parent is CX. We need to bring up CX for SMMU
* but we need both up for Adreno. On the other hand, we
* need to manage the GX rpmpd domain in the adreno driver.
* Enable CX/GX GDSCs here so that we can manage just the GX
* RPM Power Domain in the Adreno driver.
*/
power-domains = <&gpucc GPU_GX_GDSC>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_GPU_BIMC_GFX_CLK>;
clock-names = "iface", "mem", "mem_iface";
#global-interrupts = <2>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
@@ -1597,9 +1615,16 @@ blsp_i2c8: i2c@c1b8000 {
mmss_smmu: iommu@cd00000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x0cd00000 0x40000>;
clocks = <&mmcc MNOC_AHB_CLK>,
<&mmcc BIMC_SMMU_AHB_CLK>,
<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
<&mmcc BIMC_SMMU_AXI_CLK>;
clock-names = "iface-mm", "iface-smmu",
"bus-mm", "bus-smmu";
#global-interrupts = <2>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts =
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,