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drm/xe: vram addr range is expanded to bit[17:8]

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The bit field used to be [14:8] with [17:15] marked as SPARE and
defaulted to 0. So, simply expand the read to bit[17:8] assuming
the platforms using only bit[14:8] have zeros in the expanded bits.

BSpec: 54991

Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260112220330.2267122-2-fei.yang@intel.com
This commit is contained in:
Fei Yang
2026-01-12 14:03:30 -08:00
committed by Matthew Brost
parent a3753a3319
commit 6b2ff1d7c5
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/xe/xe_vram.c
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@@ -155,7 +155,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
*tile_offset = 0;
} else {
reg = xe_mmio_read32(&tile->mmio, SG_TILE_ADDR_RANGE(tile->id));
*tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
*tile_size = (u64)REG_FIELD_GET(GENMASK(17, 8), reg) * SZ_1G;
*tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
}