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scsi: ufs: core: Add quirks for VCC ramp-up delay
On some platforms, the VCC regulator has a slow ramp-up time. Add a delay after enabling VCC to ensure voltage has fully stabilized before we enable the clocks. Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Ed Tsai <ed.tsai@mediatek.com> Link: https://patch.msgid.link/20260310005230.4001904-4-ed.tsai@mediatek.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
committed by
Martin K. Petersen
parent
096cd6b7ad
commit
6ab94d0194
@@ -9952,11 +9952,13 @@ static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
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#ifdef CONFIG_PM
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static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
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{
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bool vcc_on = false;
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int ret = 0;
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if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
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!hba->dev_info.is_lu_power_on_wp) {
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ret = ufshcd_setup_vreg(hba, true);
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vcc_on = true;
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} else if (!ufshcd_is_ufs_dev_active(hba)) {
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if (!ufshcd_is_link_active(hba)) {
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ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
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@@ -9967,6 +9969,7 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
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goto vccq_lpm;
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}
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ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
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vcc_on = true;
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}
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goto out;
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@@ -9975,6 +9978,15 @@ static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
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vcc_disable:
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ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
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out:
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/*
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* On platforms with a slow VCC ramp-up, a delay is needed after
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* turning on VCC to ensure the voltage is stable before the
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* reference clock is enabled.
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*/
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if (hba->quirks & UFSHCD_QUIRK_VCC_ON_DELAY && !ret && vcc_on &&
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hba->vreg_info.vcc && !hba->vreg_info.vcc->always_on)
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usleep_range(1000, 1100);
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return ret;
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}
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#endif /* CONFIG_PM */
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@@ -690,6 +690,12 @@ enum ufshcd_quirks {
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* because it causes link startup to become unreliable.
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*/
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UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE = 1 << 26,
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/*
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* On some platforms, the VCC regulator has a slow ramp-up time. Add a
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* delay after enabling VCC to ensure it's stable.
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*/
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UFSHCD_QUIRK_VCC_ON_DELAY = 1 << 27,
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};
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enum ufshcd_caps {
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