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mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controller is not capable of swapping the bytes, the protocol is downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that it comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Suggested-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Link: https://lore.kernel.org/r/20240926141956.2386374-4-alvinzhou.tw@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
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@@ -113,6 +113,9 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
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op->cmd.opcode = (op->cmd.opcode << 8) | ext;
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op->cmd.nbytes = 2;
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}
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if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)
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op->data.swap16 = true;
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}
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/**
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@@ -140,6 +140,7 @@ enum spi_nor_option_flags {
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SNOR_F_RWW = BIT(14),
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SNOR_F_ECC = BIT(15),
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SNOR_F_NO_WP = BIT(16),
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SNOR_F_SWAP16 = BIT(17),
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};
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struct spi_nor_read_command {
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