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ARM: dts: imx: Align L2 cache-controller nodename with dtschema

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Fix dtschema validator warnings like:
    l2-cache@a02000: $nodename:0:
        'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2020-06-26 10:06:31 +02:00
committed by Shawn Guo
parent 954809fb53
commit 69cc1502a8
5 changed files with 5 additions and 5 deletions
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2
arch/arm/boot/dts/imx35.dtsi
View File

@@ -59,7 +59,7 @@ soc {
interrupt-parent = <&avic>;
ranges;
L2: l2-cache@30000000 {
L2: cache-controller@30000000 {
compatible = "arm,l210-cache";
reg = <0x30000000 0x1000>;
cache-unified;

2
arch/arm/boot/dts/imx6qdl.dtsi
View File

@@ -245,7 +245,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/imx6sl.dtsi
View File

@@ -126,7 +126,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/imx6sll.dtsi
View File

@@ -126,7 +126,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/imx6sx.dtsi
View File

@@ -179,7 +179,7 @@ intc: interrupt-controller@a01000 {
interrupt-parent = <&intc>;
};
L2: l2-cache@a02000 {
L2: cache-controller@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;