mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-16 13:41:48 -04:00
Merge branches 'clk-fixes', 'clk-renesas', 'clk-rpi', 'clk-eswin' and 'clk-mediatek' into clk-next
- ESWIN eic700 SoC clk support
- Econet EN751221 SoC clock/reset support
* clk-fixes:
clk: spacemit: ccu_mix: fix inverted condition in ccu_mix_trigger_fc()
clk: microchip: mpfs-ccc: fix out of bounds access during output registration
clk: qcom: dispcc-sm8450: use RCG2 ops for DPTX1 AUX clock source
* clk-renesas:
clk: renesas: Add support for RZ/G3L SoC
dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
clk: renesas: rzg2l: Re-enable critical module clocks during resume
clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()
clk: renesas: rzg2l: Add helper for mod clock enable/disable
clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries
clk: renesas: rzg2l: Add support for critical resets
clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}
clk: renesas: r9a06g032: Enable watchdog reset sources
clk: renesas: cpg-mssr: Use struct_size() helper
clk: renesas: r9a09g047: Add PCIe clocks and reset
clk: renesas: r9a09g057: Add PCIe clocks and reset
clk: renesas: r9a09g056: Add PCIe clocks and reset
clk: renesas: r9a09g047: Add entries for the RSPIs
clk: renesas: r9a09g056: Add clock and reset entries for RTC
clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
clk: renesas: r9a09g056: Fix ordering of module clocks array
clk: renesas: r9a09g057: Fix ordering of module clocks array
* clk-rpi:
clk: bcm: rpi: Manage clock rate in prepare/unprepare callbacks
* clk-eswin:
MAINTAINERS: Add entry for ESWIN EIC7700 clock driver
clk: eswin: Add eic7700 clock driver
clk: divider: Add devm_clk_hw_register_divider_parent_data
dt-bindings: clock: eswin: Documentation for eic7700 SoC
* clk-mediatek:
clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
dt-bindings: clock, reset: Add econet EN751221
This commit is contained in:
Stephen Boyd
@@ -32,6 +32,7 @@ properties:
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- enum:
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- airoha,en7523-scu
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- airoha,en7581-scu
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- econet,en751221-scu
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reg:
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items:
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@@ -67,7 +68,9 @@ allOf:
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- if:
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properties:
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compatible:
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const: airoha,en7581-scu
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enum:
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- airoha,en7581-scu
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- econet,en751221-scu
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then:
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properties:
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reg:
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@@ -98,3 +101,4 @@ examples:
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#reset-cells = <1>;
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};
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};
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@@ -0,0 +1,46 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Eswin EIC7700 SoC clock controller
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maintainers:
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- Yifeng Huang <huangyifeng@eswincomputing.com>
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- Xuyang Dong <dongxuyang@eswincomputing.com>
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description:
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The clock controller generates and supplies clock to all the modules
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for eic7700 SoC.
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properties:
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compatible:
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const: eswin,eic7700-clock
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reg:
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maxItems: 1
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clocks:
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items:
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- description: External 24MHz oscillator clock
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@51828000 {
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compatible = "eswin,eic7700-clock";
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reg = <0x51828000 0x300>;
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clocks = <&xtal24m>;
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#clock-cells = <1>;
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};
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@@ -28,19 +28,30 @@ properties:
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- renesas,r9a07g044-cpg # RZ/G2{L,LC}
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- renesas,r9a07g054-cpg # RZ/V2L
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- renesas,r9a08g045-cpg # RZ/G3S
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- renesas,r9a08g046-cpg # RZ/G3L
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- renesas,r9a09g011-cpg # RZ/V2M
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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minItems: 1
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items:
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- description: Clock source to CPG can be either from external clock
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input (EXCLK) or crystal oscillator (XIN/XOUT).
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- description: ETH0 TXC clock input
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- description: ETH0 RXC clock input
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- description: ETH1 TXC clock input
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- description: ETH1 RXC clock input
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clock-names:
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description:
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Clock source to CPG can be either from external clock input (EXCLK) or
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crystal oscillator (XIN/XOUT).
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const: extal
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minItems: 1
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items:
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- const: extal
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- const: eth0_txc_tx_clk
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- const: eth0_rxc_rx_clk
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- const: eth1_txc_tx_clk
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- const: eth1_rxc_rx_clk
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'#clock-cells':
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description: |
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@@ -74,6 +85,25 @@ required:
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- '#power-domain-cells'
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- '#reset-cells'
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a08g046-cpg
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then:
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properties:
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clocks:
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minItems: 5
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clock-names:
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minItems: 5
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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additionalProperties: false
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examples:
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@@ -61,6 +61,7 @@ select:
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- cirrus,ep7209-syscon2
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- cirrus,ep7209-syscon3
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- cnxt,cx92755-uc
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- econet,en751221-chip-scu
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- freecom,fsg-cs2-system-controller
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- fsl,imx93-aonmix-ns-syscfg
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- fsl,imx93-wakeupmix-syscfg
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@@ -173,6 +174,7 @@ properties:
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- cirrus,ep7209-syscon2
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- cirrus,ep7209-syscon3
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- cnxt,cx92755-uc
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- econet,en751221-chip-scu
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- freecom,fsg-cs2-system-controller
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- fsl,imx93-aonmix-ns-syscfg
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- fsl,imx93-wakeupmix-syscfg
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10
MAINTAINERS
10
MAINTAINERS
@@ -9096,6 +9096,8 @@ F: arch/mips/boot/dts/econet/
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F: arch/mips/econet/
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F: drivers/clocksource/timer-econet-en751221.c
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F: drivers/irqchip/irq-econet-en751221.c
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F: include/dt-bindings/clock/econet,en751221-scu.h
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F: include/dt-bindings/reset/econet,en751221-scu.h
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ECRYPT FILE SYSTEM
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M: Tyler Hicks <code@tyhicks.com>
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@@ -9495,6 +9497,14 @@ T: git https://github.com/eswincomputing/linux-next.git
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F: Documentation/devicetree/bindings/riscv/eswin.yaml
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F: arch/riscv/boot/dts/eswin/
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ESWIN EIC7700 CLOCK DRIVER
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M: Yifeng Huang <huangyifeng@eswincomputing.com>
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M: Xuyang Dong <dongxuyang@eswincomputing.com>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
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F: drivers/clk/eswin/
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F: include/dt-bindings/clock/eswin,eic7700-clock.h
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ET131X NETWORK DRIVER
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M: Mark Einon <mark.einon@gmail.com>
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S: Odd Fixes
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@@ -218,13 +218,13 @@ config COMMON_CLK_CS2000_CP
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If you say yes here you get support for the CS2000 clock multiplier.
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config COMMON_CLK_EN7523
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bool "Clock driver for Airoha EN7523 SoC system clocks"
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bool "Clock driver for Airoha/EcoNet SoC system clocks"
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depends on OF
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depends on ARCH_AIROHA || COMPILE_TEST
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depends on ARCH_AIROHA || ECONET || COMPILE_TEST
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default ARCH_AIROHA
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help
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This driver provides the fixed clocks and gates present on Airoha
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ARM silicon.
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and EcoNet silicon.
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config COMMON_CLK_EP93XX
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tristate "Clock driver for Cirrus Logic ep93xx SoC"
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@@ -504,6 +504,7 @@ source "drivers/clk/analogbits/Kconfig"
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source "drivers/clk/aspeed/Kconfig"
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source "drivers/clk/baikal-t1/Kconfig"
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source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/eswin/Kconfig"
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source "drivers/clk/hisilicon/Kconfig"
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source "drivers/clk/imgtec/Kconfig"
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source "drivers/clk/imx/Kconfig"
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@@ -120,6 +120,7 @@ obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/
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obj-y += bcm/
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obj-$(CONFIG_ARCH_BERLIN) += berlin/
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obj-$(CONFIG_ARCH_DAVINCI) += davinci/
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obj-$(CONFIG_COMMON_CLK_ESWIN) += eswin/
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obj-$(CONFIG_ARCH_HISI) += hisilicon/
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obj-y += imgtec/
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obj-y += imx/
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@@ -289,16 +289,31 @@ static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
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static int raspberrypi_fw_prepare(struct clk_hw *hw)
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{
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const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
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struct raspberrypi_clk_variant *variant = data->variant;
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struct raspberrypi_clk *rpi = data->rpi;
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u32 state = RPI_FIRMWARE_STATE_ENABLE_BIT;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware, data,
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RPI_FIRMWARE_SET_CLOCK_STATE, &state);
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if (ret)
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if (ret) {
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dev_err_ratelimited(rpi->dev,
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"Failed to set clock %s state to on: %d\n",
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clk_hw_get_name(hw), ret);
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return ret;
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}
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/*
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* For clocks marked with 'maximize', restore the rate to the
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* maximum after enabling. This compensates for the rate being
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* set to minimum during unprepare (see raspberrypi_fw_unprepare).
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*/
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if (variant->maximize) {
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unsigned long min_rate, max_rate;
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clk_hw_get_rate_range(hw, &min_rate, &max_rate);
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ret = raspberrypi_fw_set_rate(hw, max_rate, 0);
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}
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return ret;
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}
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@@ -307,9 +322,27 @@ static void raspberrypi_fw_unprepare(struct clk_hw *hw)
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{
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const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
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struct raspberrypi_clk *rpi = data->rpi;
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unsigned long min_rate, max_rate;
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u32 state = 0;
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int ret;
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clk_hw_get_rate_range(hw, &min_rate, &max_rate);
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/*
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* Setting the rate in unprepare is a deviation from the usual CCF
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* behavior, where unprepare only gates the clock. However, this is
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* needed, as RPI_FIRMWARE_SET_CLOCK_STATE doesn't actually power off
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* the clock on current firmware versions. Setting the rate to minimum
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* before disabling the clock is the only way to achieve meaningful
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* power savings.
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*
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* This is safe because no consumer should rely on the rate of an
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* unprepared clock. Any consumer must call clk_prepare() before use,
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* at which point the rate is either restored to maximum (for clocks
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* with the 'maximize' flag) or re-established by the consumer.
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*/
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raspberrypi_fw_set_rate(hw, min_rate, 0);
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ret = raspberrypi_clock_property(rpi->firmware, data,
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RPI_FIRMWARE_SET_CLOCK_STATE, &state);
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if (ret)
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@@ -387,9 +420,6 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi,
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}
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}
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if (variant->maximize)
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variant->min_rate = max_rate;
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if (variant->min_rate) {
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unsigned long rate;
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@@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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@@ -11,6 +12,8 @@
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#include <dt-bindings/clock/en7523-clk.h>
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#include <dt-bindings/reset/airoha,en7523-reset.h>
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#include <dt-bindings/reset/airoha,en7581-reset.h>
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#include <dt-bindings/clock/econet,en751221-scu.h>
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#include <dt-bindings/reset/econet,en751221-scu.h>
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#define RST_NR_PER_BANK 32
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@@ -33,15 +36,50 @@
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#define REG_RESET_CONTROL_PCIEHB BIT(29)
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#define REG_RESET_CONTROL_PCIE1 BIT(27)
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#define REG_RESET_CONTROL_PCIE2 BIT(26)
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#define REG_HIR 0x064
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#define REG_HIR_MASK GENMASK(31, 16)
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/* EN7581 */
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#define REG_NP_SCU_PCIC 0x88
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#define REG_NP_SCU_SSTR 0x9c
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
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#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
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#define REG_CRYPTO_CLKSRC2 0x20c
|
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/* EN751221 */
|
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#define EN751221_REG_SPI_DIV 0x0cc
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#define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8)
|
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#define EN751221_SPI_BASE 500000000
|
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#define EN751221_SPI_BASE_EN7526C 400000000
|
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#define EN751221_SPI_DIV_DEFAULT 40
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#define EN751221_REG_BUS 0x284
|
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#define EN751221_REG_BUS_MASK GENMASK(21, 12)
|
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#define EN751221_REG_SSR3 0x094
|
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#define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8)
|
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|
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#define REG_RST_CTRL2 0x830
|
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#define REG_RST_CTRL1 0x834
|
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#define EN751221_REG_RST_DMT 0x84
|
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#define EN751221_REG_RST_USB 0xec
|
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|
||||
#define EN751221_MAX_CLKS 5
|
||||
|
||||
enum en_hir {
|
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HIR_UNKNOWN = -1,
|
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HIR_TC3169 = 0,
|
||||
HIR_TC3182 = 1,
|
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HIR_RT65168 = 2,
|
||||
HIR_RT63165 = 3,
|
||||
HIR_RT63365 = 4,
|
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HIR_MT751020 = 5,
|
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HIR_MT7505 = 6,
|
||||
HIR_EN751221 = 7,
|
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HIR_EN7526C = 8,
|
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HIR_EN751627 = 9,
|
||||
HIR_EN7580 = 10,
|
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HIR_EN7528 = 11,
|
||||
HIR_EN7523 = 12,
|
||||
HIR_EN7581 = 13,
|
||||
HIR_MAX = 14,
|
||||
};
|
||||
|
||||
struct en_clk_desc {
|
||||
int id;
|
||||
@@ -93,6 +131,8 @@ static const u32 bus7581_base[] = { 600000000, 540000000 };
|
||||
static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
|
||||
static const u32 crypto_base[] = { 540000000, 480000000 };
|
||||
static const u32 emmc7581_base[] = { 200000000, 150000000 };
|
||||
/* EN751221 */
|
||||
static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
|
||||
|
||||
static const struct en_clk_desc en7523_base_clks[] = {
|
||||
{
|
||||
@@ -300,6 +340,13 @@ static const u16 en7581_rst_ofs[] = {
|
||||
REG_RST_CTRL1,
|
||||
};
|
||||
|
||||
static const u16 en751221_rst_ofs[] = {
|
||||
REG_RST_CTRL2,
|
||||
REG_RST_CTRL1,
|
||||
EN751221_REG_RST_DMT,
|
||||
EN751221_REG_RST_USB,
|
||||
};
|
||||
|
||||
static const u16 en7523_rst_map[] = {
|
||||
/* RST_CTRL2 */
|
||||
[EN7523_XPON_PHY_RST] = 0,
|
||||
@@ -405,8 +452,61 @@ static const u16 en7581_rst_map[] = {
|
||||
[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
|
||||
};
|
||||
|
||||
static const u16 en751221_rst_map[] = {
|
||||
/* RST_CTRL2 */
|
||||
[EN751221_XPON_PHY_RST] = 0,
|
||||
[EN751221_GFAST_RST] = 1,
|
||||
[EN751221_CPU_TIMER2_RST] = 2,
|
||||
[EN751221_UART3_RST] = 3,
|
||||
[EN751221_UART4_RST] = 4,
|
||||
[EN751221_UART5_RST] = 5,
|
||||
[EN751221_I2C2_RST] = 6,
|
||||
[EN751221_XSI_MAC_RST] = 7,
|
||||
[EN751221_XSI_PHY_RST] = 8,
|
||||
|
||||
/* RST_CTRL1 */
|
||||
[EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
|
||||
[EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1,
|
||||
[EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2,
|
||||
[EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3,
|
||||
[EN751221_PCM2_RST] = RST_NR_PER_BANK + 4,
|
||||
[EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5,
|
||||
[EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6,
|
||||
[EN751221_SAR_RST] = RST_NR_PER_BANK + 7,
|
||||
[EN751221_TIMER_RST] = RST_NR_PER_BANK + 8,
|
||||
[EN751221_INTC_RST] = RST_NR_PER_BANK + 9,
|
||||
[EN751221_BONDING_RST] = RST_NR_PER_BANK + 10,
|
||||
[EN751221_PCM1_RST] = RST_NR_PER_BANK + 11,
|
||||
[EN751221_UART_RST] = RST_NR_PER_BANK + 12,
|
||||
[EN751221_GPIO_RST] = RST_NR_PER_BANK + 13,
|
||||
[EN751221_GDMA_RST] = RST_NR_PER_BANK + 14,
|
||||
[EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
|
||||
[EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
|
||||
[EN751221_SFC_RST] = RST_NR_PER_BANK + 18,
|
||||
[EN751221_UART2_RST] = RST_NR_PER_BANK + 19,
|
||||
[EN751221_GDMP_RST] = RST_NR_PER_BANK + 20,
|
||||
[EN751221_FE_RST] = RST_NR_PER_BANK + 21,
|
||||
[EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
|
||||
[EN751221_GSW_RST] = RST_NR_PER_BANK + 23,
|
||||
[EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
|
||||
[EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26,
|
||||
[EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27,
|
||||
[EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
|
||||
[EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
|
||||
[EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30,
|
||||
[EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
|
||||
|
||||
/* RST_DMT */
|
||||
[EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0,
|
||||
|
||||
/* RST_USB */
|
||||
[EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6,
|
||||
[EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
|
||||
};
|
||||
|
||||
static int en7581_reset_register(struct device *dev, void __iomem *base,
|
||||
const u16 *rst_map, int nr_resets);
|
||||
const u16 *rst_map, int nr_resets,
|
||||
const u16 *rst_reg_ofs);
|
||||
|
||||
static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
|
||||
{
|
||||
@@ -604,7 +704,8 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
|
||||
en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
|
||||
|
||||
return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
|
||||
ARRAY_SIZE(en7523_rst_map));
|
||||
ARRAY_SIZE(en7523_rst_map),
|
||||
en7581_rst_ofs);
|
||||
}
|
||||
|
||||
static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
|
||||
@@ -705,7 +806,8 @@ static const struct reset_control_ops en7581_reset_ops = {
|
||||
};
|
||||
|
||||
static int en7581_reset_register(struct device *dev, void __iomem *base,
|
||||
const u16 *rst_map, int nr_resets)
|
||||
const u16 *rst_map, int nr_resets,
|
||||
const u16 *rst_reg_ofs)
|
||||
{
|
||||
struct en_rst_data *rst_data;
|
||||
|
||||
@@ -713,7 +815,7 @@ static int en7581_reset_register(struct device *dev, void __iomem *base,
|
||||
if (!rst_data)
|
||||
return -ENOMEM;
|
||||
|
||||
rst_data->bank_ofs = en7581_rst_ofs;
|
||||
rst_data->bank_ofs = rst_reg_ofs;
|
||||
rst_data->idx_map = rst_map;
|
||||
rst_data->base = base;
|
||||
|
||||
@@ -752,7 +854,107 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
|
||||
writel(val | 3, base + REG_NP_SCU_PCIC);
|
||||
|
||||
return en7581_reset_register(&pdev->dev, base, en7581_rst_map,
|
||||
ARRAY_SIZE(en7581_rst_map));
|
||||
ARRAY_SIZE(en7581_rst_map),
|
||||
en7581_rst_ofs);
|
||||
}
|
||||
|
||||
static enum en_hir get_hw_id(void __iomem *np_base)
|
||||
{
|
||||
u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
|
||||
|
||||
if (val < HIR_MAX)
|
||||
return (enum en_hir)val;
|
||||
|
||||
pr_warn("Unable to determine EcoNet SoC\n");
|
||||
|
||||
return HIR_UNKNOWN;
|
||||
}
|
||||
|
||||
static void en751221_try_register_clk(struct device *dev, int key,
|
||||
struct clk_hw_onecell_data *clk_data,
|
||||
const char *name, u32 rate)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
|
||||
if (WARN_ON_ONCE(key >= EN751221_MAX_CLKS))
|
||||
return;
|
||||
|
||||
hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
|
||||
if (IS_ERR(hw))
|
||||
pr_err("Failed to register clk %s: %pe\n", name, hw);
|
||||
else
|
||||
clk_data->hws[key] = hw;
|
||||
}
|
||||
|
||||
static void en751221_register_clocks(struct device *dev,
|
||||
struct clk_hw_onecell_data *clk_data,
|
||||
struct regmap *map, void __iomem *np_base)
|
||||
{
|
||||
enum en_hir hid = get_hw_id(np_base);
|
||||
struct clk_hw *hw;
|
||||
u32 rate;
|
||||
u32 div;
|
||||
int err;
|
||||
|
||||
/* PCI */
|
||||
hw = en7523_register_pcie_clk(dev, np_base);
|
||||
clk_data->hws[EN751221_CLK_PCIE] = hw;
|
||||
|
||||
/* SPI */
|
||||
rate = EN751221_SPI_BASE;
|
||||
if (hid == HIR_EN7526C)
|
||||
rate = EN751221_SPI_BASE_EN7526C;
|
||||
|
||||
err = regmap_read(map, EN751221_REG_SPI_DIV, &div);
|
||||
if (err) {
|
||||
pr_err("Failed reading fixed clk div %s: %d\n",
|
||||
"spi", err);
|
||||
} else {
|
||||
div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2;
|
||||
if (!div)
|
||||
div = EN751221_SPI_DIV_DEFAULT;
|
||||
|
||||
en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data,
|
||||
"spi", rate / div);
|
||||
}
|
||||
|
||||
/* BUS */
|
||||
rate = FIELD_GET(EN751221_REG_BUS_MASK,
|
||||
readl(np_base + EN751221_REG_BUS));
|
||||
rate *= 1000000;
|
||||
en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus",
|
||||
rate);
|
||||
|
||||
/* CPU */
|
||||
en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu",
|
||||
rate * 4);
|
||||
|
||||
/* GSW */
|
||||
rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK,
|
||||
readl(np_base + EN751221_REG_SSR3));
|
||||
en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw",
|
||||
gsw751221_base[rate]);
|
||||
}
|
||||
|
||||
static int en751221_clk_hw_init(struct platform_device *pdev,
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
struct regmap *map;
|
||||
void __iomem *base;
|
||||
|
||||
map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu");
|
||||
if (IS_ERR(map))
|
||||
return PTR_ERR(map);
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
en751221_register_clocks(&pdev->dev, clk_data, map, base);
|
||||
|
||||
return en7581_reset_register(&pdev->dev, base, en751221_rst_map,
|
||||
ARRAY_SIZE(en751221_rst_map),
|
||||
en751221_rst_ofs);
|
||||
}
|
||||
|
||||
static int en7523_clk_probe(struct platform_device *pdev)
|
||||
@@ -799,9 +1001,20 @@ static const struct en_clk_soc_data en7581_data = {
|
||||
.hw_init = en7581_clk_hw_init,
|
||||
};
|
||||
|
||||
static const struct en_clk_soc_data en751221_data = {
|
||||
.num_clocks = EN751221_MAX_CLKS,
|
||||
.pcie_ops = {
|
||||
.is_enabled = en7523_pci_is_enabled,
|
||||
.prepare = en7523_pci_prepare,
|
||||
.unprepare = en7523_pci_unprepare,
|
||||
},
|
||||
.hw_init = en751221_clk_hw_init,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_en7523[] = {
|
||||
{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
|
||||
{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
|
||||
{ .compatible = "econet,en751221-scu", .data = &en751221_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
15
drivers/clk/eswin/Kconfig
Normal file
15
drivers/clk/eswin/Kconfig
Normal file
@@ -0,0 +1,15 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
config COMMON_CLK_ESWIN
|
||||
bool
|
||||
|
||||
config COMMON_CLK_EIC7700
|
||||
tristate "EIC7700 Clock Driver"
|
||||
depends on ARCH_ESWIN || COMPILE_TEST
|
||||
select COMMON_CLK_ESWIN
|
||||
default ARCH_ESWIN
|
||||
help
|
||||
This driver provides support for clock controller on ESWIN EIC7700
|
||||
SoC. The clock controller generates and supplies clocks to various
|
||||
peripherals within the SoC.
|
||||
Say yes here to support the clock controller on the EIC7700 SoC.
|
||||
8
drivers/clk/eswin/Makefile
Normal file
8
drivers/clk/eswin/Makefile
Normal file
@@ -0,0 +1,8 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Eswin Clock specific Makefile
|
||||
#
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o
|
||||
1376
drivers/clk/eswin/clk-eic7700.c
Normal file
1376
drivers/clk/eswin/clk-eic7700.c
Normal file
File diff suppressed because it is too large
Load Diff
586
drivers/clk/eswin/clk.c
Normal file
586
drivers/clk/eswin/clk.c
Normal file
@@ -0,0 +1,586 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
|
||||
* All rights reserved.
|
||||
*
|
||||
* Authors:
|
||||
* Yifeng Huang <huangyifeng@eswincomputing.com>
|
||||
* Xuyang Dong <dongxuyang@eswincomputing.com>
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/math.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define PLL_EN_MASK GENMASK(1, 0)
|
||||
#define PLL_REFDIV_MASK GENMASK(17, 12)
|
||||
#define PLL_FBDIV_MASK GENMASK(31, 20)
|
||||
#define PLL_FRAC_MASK GENMASK(27, 4)
|
||||
#define PLL_POSTDIV1_MASK GENMASK(10, 8)
|
||||
#define PLL_POSTDIV2_MASK GENMASK(18, 16)
|
||||
|
||||
struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev,
|
||||
size_t nr_clks)
|
||||
{
|
||||
struct eswin_clock_data *eclk_data;
|
||||
|
||||
eclk_data = devm_kzalloc(&pdev->dev,
|
||||
struct_size(eclk_data, clk_data.hws, nr_clks),
|
||||
GFP_KERNEL);
|
||||
if (!eclk_data)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
eclk_data->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(eclk_data->base))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
eclk_data->clk_data.num = nr_clks;
|
||||
spin_lock_init(&eclk_data->lock);
|
||||
|
||||
return eclk_data;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_init);
|
||||
|
||||
/**
|
||||
* eswin_calc_pll - calculate PLL values
|
||||
* @frac_val: fractional divider
|
||||
* @fbdiv_val: feedback divider
|
||||
* @rate: reference rate
|
||||
* @parent_rate: parent rate
|
||||
*
|
||||
* Calculate PLL values for frac and fbdiv:
|
||||
* fbdiv = rate * 4 / parent_rate
|
||||
* frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate
|
||||
*/
|
||||
static void eswin_calc_pll(u32 *frac_val, u32 *fbdiv_val, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
u32 rem;
|
||||
u64 tmp;
|
||||
|
||||
/* step 1: rate * 4 */
|
||||
tmp = rate * 4;
|
||||
/* step 2: use do_div() to get the quotient(tmp) and remainder(rem) */
|
||||
rem = do_div(tmp, (u32)parent_rate);
|
||||
/* fbdiv = rate * 4 / parent_rate */
|
||||
*fbdiv_val = (u32)tmp;
|
||||
/*
|
||||
* step 3: rem << 24
|
||||
* 24: 24-bit fractional accuracy
|
||||
*/
|
||||
tmp = (u64)rem << 24;
|
||||
/* step 4: use do_div() to get the quotient(tmp) */
|
||||
do_div(tmp, (u32)parent_rate);
|
||||
/* frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate */
|
||||
*frac_val = (u32)tmp;
|
||||
}
|
||||
|
||||
static inline struct eswin_clk_pll *to_pll_clk(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct eswin_clk_pll, hw);
|
||||
}
|
||||
|
||||
static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct eswin_clk_pll *clk = to_pll_clk(hw);
|
||||
u32 frac_val, fbdiv_val, val, mask;
|
||||
int ret;
|
||||
|
||||
eswin_calc_pll(&frac_val, &fbdiv_val, rate, parent_rate);
|
||||
|
||||
/* First, disable pll */
|
||||
val = readl_relaxed(clk->ctrl_reg0);
|
||||
val &= ~PLL_EN_MASK;
|
||||
val |= FIELD_PREP(PLL_EN_MASK, 0);
|
||||
writel_relaxed(val, clk->ctrl_reg0);
|
||||
|
||||
val = readl_relaxed(clk->ctrl_reg0);
|
||||
val &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK);
|
||||
val |= FIELD_PREP(PLL_FBDIV_MASK, fbdiv_val);
|
||||
val |= FIELD_PREP(PLL_REFDIV_MASK, 1);
|
||||
writel_relaxed(val, clk->ctrl_reg0);
|
||||
|
||||
val = readl_relaxed(clk->ctrl_reg1);
|
||||
val &= ~PLL_FRAC_MASK;
|
||||
val |= FIELD_PREP(PLL_FRAC_MASK, frac_val);
|
||||
writel_relaxed(val, clk->ctrl_reg1);
|
||||
|
||||
val = readl_relaxed(clk->ctrl_reg2);
|
||||
val &= ~(PLL_POSTDIV1_MASK | PLL_POSTDIV2_MASK);
|
||||
val |= FIELD_PREP(PLL_POSTDIV1_MASK, 1);
|
||||
val |= FIELD_PREP(PLL_POSTDIV2_MASK, 1);
|
||||
writel_relaxed(val, clk->ctrl_reg2);
|
||||
|
||||
/* Last, enable pll */
|
||||
val = readl_relaxed(clk->ctrl_reg0);
|
||||
val &= ~PLL_EN_MASK;
|
||||
val |= FIELD_PREP(PLL_EN_MASK, 1);
|
||||
writel_relaxed(val, clk->ctrl_reg0);
|
||||
|
||||
/* Usually the pll will lock in 50us */
|
||||
mask = GENMASK(clk->lock_shift + clk->lock_width - 1, clk->lock_shift);
|
||||
ret = readl_poll_timeout(clk->status_reg, val, val & mask, 1, 50 * 2);
|
||||
if (ret)
|
||||
pr_err("failed to lock the pll!\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct eswin_clk_pll *clk = to_pll_clk(hw);
|
||||
u64 fbdiv_val, frac_val, tmp;
|
||||
u32 rem, val;
|
||||
|
||||
val = readl_relaxed(clk->ctrl_reg0);
|
||||
val &= PLL_FBDIV_MASK;
|
||||
fbdiv_val = (val >> clk->fbdiv_shift);
|
||||
|
||||
val = readl_relaxed(clk->ctrl_reg1);
|
||||
val &= PLL_FRAC_MASK;
|
||||
frac_val = (val >> clk->frac_shift);
|
||||
|
||||
/* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */
|
||||
tmp = parent_rate * frac_val;
|
||||
rem = do_div(tmp, BIT(24));
|
||||
if (rem)
|
||||
tmp = parent_rate * fbdiv_val + tmp + 1;
|
||||
else
|
||||
tmp = parent_rate * fbdiv_val + tmp;
|
||||
|
||||
do_div(tmp, 4);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static int clk_pll_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct eswin_clk_pll *clk = to_pll_clk(hw);
|
||||
|
||||
req->rate = clamp(req->rate, clk->min_rate, clk->max_rate);
|
||||
req->min_rate = clk->min_rate;
|
||||
req->max_rate = clk->max_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int eswin_clk_register_fixed_rate(struct device *dev,
|
||||
struct eswin_fixed_rate_clock *clks,
|
||||
int nums, struct eswin_clock_data *data)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk_hw = devm_clk_hw_register_fixed_rate(dev, clks[i].name,
|
||||
NULL, clks[i].flags,
|
||||
clks[i].rate);
|
||||
if (IS_ERR(clk_hw))
|
||||
return PTR_ERR(clk_hw);
|
||||
|
||||
clks[i].hw = *clk_hw;
|
||||
data->clk_data.hws[clks[i].id] = clk_hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_rate);
|
||||
|
||||
static const struct clk_ops eswin_clk_pll_ops = {
|
||||
.set_rate = clk_pll_set_rate,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.determine_rate = clk_pll_determine_rate,
|
||||
};
|
||||
|
||||
int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks,
|
||||
int nums, struct eswin_clock_data *data)
|
||||
{
|
||||
struct eswin_clk_pll *p_clk = NULL;
|
||||
struct clk_init_data init;
|
||||
struct clk_hw *clk_hw;
|
||||
int i, ret;
|
||||
|
||||
p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
|
||||
if (!p_clk)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
p_clk->id = clks[i].id;
|
||||
p_clk->ctrl_reg0 = data->base + clks[i].ctrl_reg0;
|
||||
p_clk->fbdiv_shift = clks[i].fbdiv_shift;
|
||||
|
||||
p_clk->ctrl_reg1 = data->base + clks[i].ctrl_reg1;
|
||||
p_clk->frac_shift = clks[i].frac_shift;
|
||||
|
||||
p_clk->ctrl_reg2 = data->base + clks[i].ctrl_reg2;
|
||||
|
||||
p_clk->status_reg = data->base + clks[i].status_reg;
|
||||
p_clk->lock_shift = clks[i].lock_shift;
|
||||
p_clk->lock_width = clks[i].lock_width;
|
||||
|
||||
p_clk->max_rate = clks[i].max_rate;
|
||||
p_clk->min_rate = clks[i].min_rate;
|
||||
|
||||
init.name = clks[i].name;
|
||||
init.flags = 0;
|
||||
init.parent_data = clks[i].parent_data;
|
||||
init.num_parents = 1;
|
||||
init.ops = &eswin_clk_pll_ops;
|
||||
p_clk->hw.init = &init;
|
||||
|
||||
clk_hw = &p_clk->hw;
|
||||
|
||||
ret = devm_clk_hw_register(dev, clk_hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clks[i].hw = *clk_hw;
|
||||
data->clk_data.hws[clks[i].id] = clk_hw;
|
||||
p_clk++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_register_pll);
|
||||
|
||||
int eswin_clk_register_fixed_factor(struct device *dev,
|
||||
struct eswin_fixed_factor_clock *clks,
|
||||
int nums, struct eswin_clock_data *data)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk_hw = devm_clk_hw_register_fixed_factor_index(dev, clks[i].name,
|
||||
clks[i].parent_data->index,
|
||||
clks[i].flags, clks[i].mult,
|
||||
clks[i].div);
|
||||
|
||||
if (IS_ERR(clk_hw))
|
||||
return PTR_ERR(clk_hw);
|
||||
|
||||
clks[i].hw = *clk_hw;
|
||||
data->clk_data.hws[clks[i].id] = clk_hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_factor);
|
||||
|
||||
int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks,
|
||||
int nums, struct eswin_clock_data *data)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk_hw = devm_clk_hw_register_mux_parent_data_table(dev, clks[i].name,
|
||||
clks[i].parent_data,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags,
|
||||
data->base + clks[i].reg,
|
||||
clks[i].shift, clks[i].width,
|
||||
clks[i].mux_flags,
|
||||
clks[i].table, &data->lock);
|
||||
|
||||
if (IS_ERR(clk_hw))
|
||||
return PTR_ERR(clk_hw);
|
||||
|
||||
clks[i].hw = *clk_hw;
|
||||
data->clk_data.hws[clks[i].id] = clk_hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_register_mux);
|
||||
|
||||
static unsigned int _eswin_get_val(unsigned int div, unsigned long flags,
|
||||
u8 width)
|
||||
{
|
||||
unsigned int maxdiv;
|
||||
|
||||
maxdiv = clk_div_mask(width);
|
||||
div = div > maxdiv ? maxdiv : div;
|
||||
|
||||
if (flags & ESWIN_PRIV_DIV_MIN_2)
|
||||
return (div < 2) ? 2 : div;
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
static unsigned int eswin_div_get_val(unsigned long rate,
|
||||
unsigned long parent_rate, u8 width,
|
||||
unsigned long flags)
|
||||
{
|
||||
unsigned int div;
|
||||
|
||||
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
|
||||
|
||||
return _eswin_get_val(div, flags, width);
|
||||
}
|
||||
|
||||
static inline struct eswin_divider_clock *to_div_clk(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct eswin_divider_clock, hw);
|
||||
}
|
||||
|
||||
static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct eswin_divider_clock *dclk = to_div_clk(hw);
|
||||
unsigned long flags;
|
||||
unsigned int value;
|
||||
u32 val;
|
||||
|
||||
value = eswin_div_get_val(rate, parent_rate, dclk->width,
|
||||
dclk->priv_flag);
|
||||
|
||||
spin_lock_irqsave(dclk->lock, flags);
|
||||
|
||||
val = readl_relaxed(dclk->ctrl_reg);
|
||||
val &= ~(clk_div_mask(dclk->width) << dclk->shift);
|
||||
val |= (u32)value << dclk->shift;
|
||||
writel_relaxed(val, dclk->ctrl_reg);
|
||||
|
||||
spin_unlock_irqrestore(dclk->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct eswin_divider_clock *dclk = to_div_clk(hw);
|
||||
unsigned int div, val;
|
||||
|
||||
val = readl_relaxed(dclk->ctrl_reg) >> dclk->shift;
|
||||
val &= clk_div_mask(dclk->width);
|
||||
div = _eswin_get_val(val, dclk->priv_flag, dclk->width);
|
||||
|
||||
return DIV_ROUND_UP_ULL((u64)parent_rate, div);
|
||||
}
|
||||
|
||||
static int eswin_clk_bestdiv(unsigned long rate,
|
||||
unsigned long best_parent_rate, u8 width,
|
||||
unsigned long flags)
|
||||
{
|
||||
unsigned long bestdiv, up_rate, down_rate;
|
||||
int up, down;
|
||||
|
||||
if (!rate)
|
||||
rate = 1;
|
||||
|
||||
/* closest round */
|
||||
up = DIV_ROUND_UP_ULL((u64)best_parent_rate, rate);
|
||||
down = best_parent_rate / rate;
|
||||
|
||||
up_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, up);
|
||||
down_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, down);
|
||||
|
||||
bestdiv = (rate - up_rate) <= (down_rate - rate) ? up : down;
|
||||
|
||||
return bestdiv;
|
||||
}
|
||||
|
||||
static int clk_div_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct eswin_divider_clock *dclk = to_div_clk(hw);
|
||||
int div;
|
||||
|
||||
div = eswin_clk_bestdiv(req->rate, req->best_parent_rate, dclk->width,
|
||||
dclk->priv_flag);
|
||||
div = _eswin_get_val(div, dclk->priv_flag, dclk->width);
|
||||
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops eswin_clk_div_ops = {
|
||||
.set_rate = clk_div_set_rate,
|
||||
.recalc_rate = clk_div_recalc_rate,
|
||||
.determine_rate = clk_div_determine_rate,
|
||||
};
|
||||
|
||||
struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id,
|
||||
const char *name,
|
||||
const struct clk_hw *parent_hw,
|
||||
unsigned long flags, void __iomem *reg,
|
||||
u8 shift, u8 width,
|
||||
unsigned long clk_divider_flags,
|
||||
unsigned long priv_flag, spinlock_t *lock)
|
||||
{
|
||||
struct eswin_divider_clock *dclk;
|
||||
struct clk_init_data init;
|
||||
struct clk_hw *clk_hw;
|
||||
int ret;
|
||||
|
||||
dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL);
|
||||
if (!dclk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &eswin_clk_div_ops;
|
||||
init.flags = flags;
|
||||
init.parent_hws = &parent_hw;
|
||||
init.num_parents = 1;
|
||||
|
||||
/* struct clk_divider assignments */
|
||||
dclk->id = id;
|
||||
dclk->ctrl_reg = reg;
|
||||
dclk->shift = shift;
|
||||
dclk->width = width;
|
||||
dclk->div_flags = clk_divider_flags;
|
||||
dclk->priv_flag = priv_flag;
|
||||
dclk->lock = lock;
|
||||
dclk->hw.init = &init;
|
||||
|
||||
/* register the clock */
|
||||
clk_hw = &dclk->hw;
|
||||
ret = devm_clk_hw_register(dev, clk_hw);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register divider clock!\n");
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return clk_hw;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_register_clkdiv);
|
||||
|
||||
int eswin_clk_register_divider(struct device *dev,
|
||||
struct eswin_divider_clock *clks,
|
||||
int nums, struct eswin_clock_data *data)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk_hw = devm_clk_hw_register_divider_parent_data(dev, clks[i].name,
|
||||
clks[i].parent_data,
|
||||
clks[i].flags,
|
||||
data->base + clks[i].reg,
|
||||
clks[i].shift, clks[i].width,
|
||||
clks[i].div_flags, &data->lock);
|
||||
|
||||
if (IS_ERR(clk_hw))
|
||||
return PTR_ERR(clk_hw);
|
||||
|
||||
clks[i].hw = *clk_hw;
|
||||
data->clk_data.hws[clks[i].id] = clk_hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_register_divider);
|
||||
|
||||
int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks,
|
||||
int nums, struct eswin_clock_data *data)
|
||||
{
|
||||
struct clk_hw *clk_hw;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk_hw = devm_clk_hw_register_gate_parent_data(dev, clks[i].name,
|
||||
clks[i].parent_data,
|
||||
clks[i].flags,
|
||||
data->base + clks[i].reg,
|
||||
clks[i].bit_idx, clks[i].gate_flags,
|
||||
&data->lock);
|
||||
|
||||
if (IS_ERR(clk_hw))
|
||||
return PTR_ERR(clk_hw);
|
||||
|
||||
clks[i].hw = *clk_hw;
|
||||
data->clk_data.hws[clks[i].id] = clk_hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_register_gate);
|
||||
|
||||
int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks,
|
||||
int nums, struct eswin_clock_data *data)
|
||||
{
|
||||
struct eswin_clk_info *info;
|
||||
const struct clk_hw *phw = NULL;
|
||||
struct clk_hw *hw;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
info = &clks[i];
|
||||
switch (info->type) {
|
||||
case CLK_FIXED_FACTOR: {
|
||||
const struct eswin_fixed_factor_clock *factor;
|
||||
|
||||
factor = &info->data.factor;
|
||||
phw = data->clk_data.hws[info->pid];
|
||||
hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, factor->name, phw,
|
||||
factor->flags,
|
||||
factor->mult,
|
||||
factor->div);
|
||||
break;
|
||||
}
|
||||
case CLK_MUX: {
|
||||
const struct eswin_mux_clock *mux = &info->data.mux;
|
||||
|
||||
hw = devm_clk_hw_register_mux_parent_data_table(dev, mux->name,
|
||||
mux->parent_data,
|
||||
mux->num_parents,
|
||||
mux->flags,
|
||||
data->base + mux->reg,
|
||||
mux->shift, mux->width,
|
||||
mux->mux_flags,
|
||||
mux->table, &data->lock);
|
||||
break;
|
||||
}
|
||||
case CLK_DIVIDER: {
|
||||
const struct eswin_divider_clock *div = &info->data.div;
|
||||
|
||||
phw = data->clk_data.hws[info->pid];
|
||||
if (div->priv_flag)
|
||||
hw = eswin_register_clkdiv(dev, div->id, div->name, phw,
|
||||
div->flags, data->base + div->reg,
|
||||
div->shift, div->width, div->div_flags,
|
||||
div->priv_flag, &data->lock);
|
||||
else
|
||||
hw = devm_clk_hw_register_divider_parent_hw(dev, div->name, phw,
|
||||
div->flags,
|
||||
data->base + div->reg,
|
||||
div->shift, div->width,
|
||||
div->div_flags,
|
||||
&data->lock);
|
||||
break;
|
||||
}
|
||||
case CLK_GATE: {
|
||||
const struct eswin_gate_clock *gate = &info->data.gate;
|
||||
|
||||
phw = data->clk_data.hws[info->pid];
|
||||
hw = devm_clk_hw_register_gate_parent_hw(dev, gate->name, phw,
|
||||
gate->flags,
|
||||
data->base + gate->reg,
|
||||
gate->bit_idx, gate->gate_flags,
|
||||
&data->lock);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
dev_err(dev, "Unidentifiable clock type!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (IS_ERR(hw))
|
||||
return PTR_ERR(hw);
|
||||
|
||||
info->hw = *hw;
|
||||
data->clk_data.hws[info->id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(eswin_clk_register_clks);
|
||||
340
drivers/clk/eswin/common.h
Normal file
340
drivers/clk/eswin/common.h
Normal file
@@ -0,0 +1,340 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
|
||||
* All rights reserved.
|
||||
*
|
||||
* Authors:
|
||||
* Yifeng Huang <huangyifeng@eswincomputing.com>
|
||||
* Xuyang Dong <dongxuyang@eswincomputing.com>
|
||||
*/
|
||||
|
||||
#ifndef __ESWIN_COMMON_H__
|
||||
#define __ESWIN_COMMON_H__
|
||||
|
||||
#define APLL_HIGH_FREQ 983040000
|
||||
#define APLL_LOW_FREQ 225792000
|
||||
#define PLL_HIGH_FREQ 1800000000
|
||||
#define PLL_LOW_FREQ 24000000
|
||||
|
||||
/*
|
||||
* ESWIN_PRIV_DIV_MIN_2: If ESWIN_PRIV_DIV_MIN_2 is set, the minimum value of
|
||||
* the register is 2, i.e. the minimum division ratio is 2.
|
||||
*/
|
||||
#define ESWIN_PRIV_DIV_MIN_2 BIT(0)
|
||||
|
||||
enum eswin_clk_type {
|
||||
CLK_FIXED_FACTOR,
|
||||
CLK_MUX,
|
||||
CLK_DIVIDER,
|
||||
CLK_GATE,
|
||||
};
|
||||
|
||||
struct eswin_clock_data {
|
||||
void __iomem *base;
|
||||
struct clk_hw *original_clk;
|
||||
struct notifier_block pll_nb;
|
||||
spinlock_t lock; /* protect register read-modify-write cycle */
|
||||
struct clk_hw_onecell_data clk_data;
|
||||
};
|
||||
|
||||
struct eswin_divider_clock {
|
||||
struct clk_hw hw;
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const struct clk_parent_data *parent_data;
|
||||
void __iomem *ctrl_reg; /* register address of the divider clock */
|
||||
unsigned long flags;
|
||||
unsigned long reg; /* register offset */
|
||||
u8 shift;
|
||||
u8 width;
|
||||
unsigned long div_flags;
|
||||
unsigned long priv_flag;
|
||||
spinlock_t *lock; /* protect register read-modify-write cycle */
|
||||
};
|
||||
|
||||
struct eswin_fixed_rate_clock {
|
||||
struct clk_hw hw;
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
unsigned long flags;
|
||||
unsigned long rate;
|
||||
};
|
||||
|
||||
struct eswin_fixed_factor_clock {
|
||||
struct clk_hw hw;
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const struct clk_parent_data *parent_data;
|
||||
unsigned long mult;
|
||||
unsigned long div;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
struct eswin_gate_clock {
|
||||
struct clk_hw hw;
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const struct clk_parent_data *parent_data;
|
||||
unsigned long flags;
|
||||
unsigned long reg;
|
||||
u8 bit_idx;
|
||||
u8 gate_flags;
|
||||
};
|
||||
|
||||
struct eswin_mux_clock {
|
||||
struct clk_hw hw;
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const struct clk_parent_data *parent_data;
|
||||
u8 num_parents;
|
||||
unsigned long flags;
|
||||
unsigned long reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 mux_flags;
|
||||
u32 *table;
|
||||
};
|
||||
|
||||
struct eswin_pll_clock {
|
||||
struct clk_hw hw;
|
||||
u32 id;
|
||||
const char *name;
|
||||
const struct clk_parent_data *parent_data;
|
||||
const u32 ctrl_reg0;
|
||||
const u8 fbdiv_shift;
|
||||
|
||||
const u32 ctrl_reg1;
|
||||
const u8 frac_shift;
|
||||
|
||||
const u32 ctrl_reg2;
|
||||
|
||||
const u32 status_reg;
|
||||
const u8 lock_shift;
|
||||
const u8 lock_width;
|
||||
|
||||
const u64 max_rate;
|
||||
const u64 min_rate;
|
||||
};
|
||||
|
||||
struct eswin_clk_pll {
|
||||
struct clk_hw hw;
|
||||
u32 id;
|
||||
void __iomem *ctrl_reg0;
|
||||
u8 fbdiv_shift;
|
||||
|
||||
void __iomem *ctrl_reg1;
|
||||
u8 frac_shift;
|
||||
|
||||
void __iomem *ctrl_reg2;
|
||||
|
||||
void __iomem *status_reg;
|
||||
u8 lock_shift;
|
||||
u8 lock_width;
|
||||
|
||||
u64 max_rate;
|
||||
u64 min_rate;
|
||||
};
|
||||
|
||||
struct eswin_clk_info {
|
||||
unsigned int type;
|
||||
unsigned int pid;
|
||||
unsigned int id;
|
||||
struct clk_hw hw;
|
||||
union {
|
||||
struct eswin_divider_clock div;
|
||||
struct eswin_fixed_factor_clock factor;
|
||||
struct eswin_gate_clock gate;
|
||||
struct eswin_mux_clock mux;
|
||||
} data;
|
||||
};
|
||||
|
||||
struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev,
|
||||
size_t nr_clks);
|
||||
int eswin_clk_register_fixed_rate(struct device *dev,
|
||||
struct eswin_fixed_rate_clock *clks,
|
||||
int nums, struct eswin_clock_data *data);
|
||||
int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks,
|
||||
int nums, struct eswin_clock_data *data);
|
||||
int eswin_clk_register_fixed_factor(struct device *dev,
|
||||
struct eswin_fixed_factor_clock *clks,
|
||||
int nums, struct eswin_clock_data *data);
|
||||
int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks,
|
||||
int nums, struct eswin_clock_data *data);
|
||||
int eswin_clk_register_divider(struct device *dev,
|
||||
struct eswin_divider_clock *clks,
|
||||
int nums, struct eswin_clock_data *data);
|
||||
int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks,
|
||||
int nums, struct eswin_clock_data *data);
|
||||
int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks,
|
||||
int nums, struct eswin_clock_data *data);
|
||||
struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id,
|
||||
const char *name,
|
||||
const struct clk_hw *parent_hw,
|
||||
unsigned long flags, void __iomem *reg,
|
||||
u8 shift, u8 width,
|
||||
unsigned long clk_divider_flags,
|
||||
unsigned long priv_flag, spinlock_t *lock);
|
||||
|
||||
#define ESWIN_DIV(_id, _name, _pdata, _flags, _reg, _shift, _width, \
|
||||
_dflags, _pflag) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_data = _pdata, \
|
||||
.flags = _flags, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.div_flags = _dflags, \
|
||||
.priv_flag = _pflag, \
|
||||
}
|
||||
|
||||
#define ESWIN_DIV_TYPE(_id, _name, _pid, _flags, _reg, _shift, _width, \
|
||||
_dflags, _pflag) \
|
||||
{ \
|
||||
.type = CLK_DIVIDER, \
|
||||
.pid = _pid, \
|
||||
.id = _id, \
|
||||
.data = { \
|
||||
.div = { \
|
||||
.name = _name, \
|
||||
.flags = _flags, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.div_flags = _dflags, \
|
||||
.priv_flag = _pflag, \
|
||||
}, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define ESWIN_FACTOR(_id, _name, _pdata, _mult, _div, _flags) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_data = _pdata, \
|
||||
.mult = _mult, \
|
||||
.div = _div, \
|
||||
.flags = _flags, \
|
||||
}
|
||||
|
||||
#define ESWIN_FACTOR_TYPE(_id, _name, _pid, _mult, _div, _flags) \
|
||||
{ \
|
||||
.type = CLK_FIXED_FACTOR, \
|
||||
.pid = _pid, \
|
||||
.id = _id, \
|
||||
.data = { \
|
||||
.factor = { \
|
||||
.name = _name, \
|
||||
.mult = _mult, \
|
||||
.div = _div, \
|
||||
.flags = _flags, \
|
||||
}, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define ESWIN_FIXED(_id, _name, _flags, _rate) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.flags = _flags, \
|
||||
.rate = _rate, \
|
||||
}
|
||||
|
||||
#define ESWIN_GATE(_id, _name, _pdata, _flags, _reg, _idx, _gflags) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_data = _pdata, \
|
||||
.flags = _flags, \
|
||||
.reg = _reg, \
|
||||
.bit_idx = _idx, \
|
||||
.gate_flags = _gflags, \
|
||||
}
|
||||
|
||||
#define ESWIN_GATE_TYPE(_id, _name, _pid, _flags, _reg, _idx, _gflags) \
|
||||
{ \
|
||||
.type = CLK_GATE, \
|
||||
.pid = _pid, \
|
||||
.id = _id, \
|
||||
.data = { \
|
||||
.gate = { \
|
||||
.name = _name, \
|
||||
.flags = _flags, \
|
||||
.reg = _reg, \
|
||||
.bit_idx = _idx, \
|
||||
.gate_flags = _gflags, \
|
||||
}, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define ESWIN_MUX(_id, _name, _pdata, _num_parents, _flags, _reg, \
|
||||
_shift, _width, _mflags) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_data = _pdata, \
|
||||
.num_parents = _num_parents, \
|
||||
.flags = _flags, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.mux_flags = _mflags, \
|
||||
.table = NULL, \
|
||||
}
|
||||
|
||||
#define ESWIN_MUX_TBL(_id, _name, _pdata, _num_parents, _flags, _reg, \
|
||||
_shift, _width, _mflags, _table) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_data = _pdata, \
|
||||
.num_parents = _num_parents, \
|
||||
.flags = _flags, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.mux_flags = _mflags, \
|
||||
.table = _table, \
|
||||
}
|
||||
|
||||
#define ESWIN_MUX_TYPE(_id, _name, _pdata, _num_parents, _flags, _reg, \
|
||||
_shift, _width, _mflags, _table) \
|
||||
{ \
|
||||
.type = CLK_MUX, \
|
||||
.id = _id, \
|
||||
.data = { \
|
||||
.mux = { \
|
||||
.name = _name, \
|
||||
.parent_data = _pdata, \
|
||||
.num_parents = _num_parents, \
|
||||
.flags = _flags, \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.mux_flags = _mflags, \
|
||||
.table = _table, \
|
||||
}, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define ESWIN_PLL(_id, _name, _pdata, _reg0, _fb_shift, _reg1, \
|
||||
_frac_shift, _reg2, _reg, _lock_shift, _lock_width, \
|
||||
_max_rate, _min_rate) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_data = _pdata, \
|
||||
.ctrl_reg0 = _reg0, \
|
||||
.fbdiv_shift = _fb_shift, \
|
||||
.ctrl_reg1 = _reg1, \
|
||||
.frac_shift = _frac_shift, \
|
||||
.ctrl_reg2 = _reg2, \
|
||||
.status_reg = _reg, \
|
||||
.lock_shift = _lock_shift, \
|
||||
.lock_width = _lock_width, \
|
||||
.max_rate = _max_rate, \
|
||||
.min_rate = _min_rate, \
|
||||
}
|
||||
|
||||
#endif /* __ESWIN_COMMON_H__ */
|
||||
@@ -39,6 +39,7 @@ config CLK_RENESAS
|
||||
select CLK_R9A07G044 if ARCH_R9A07G044
|
||||
select CLK_R9A07G054 if ARCH_R9A07G054
|
||||
select CLK_R9A08G045 if ARCH_R9A08G045
|
||||
select CLK_R9A08G046 if ARCH_R9A08G046
|
||||
select CLK_R9A09G011 if ARCH_R9A09G011
|
||||
select CLK_R9A09G047 if ARCH_R9A09G047
|
||||
select CLK_R9A09G056 if ARCH_R9A09G056
|
||||
@@ -194,6 +195,10 @@ config CLK_R9A08G045
|
||||
bool "RZ/G3S clock support" if COMPILE_TEST
|
||||
select CLK_RZG2L
|
||||
|
||||
config CLK_R9A08G046
|
||||
bool "RZ/G3L clock support" if COMPILE_TEST
|
||||
select CLK_RZG2L
|
||||
|
||||
config CLK_R9A09G011
|
||||
bool "RZ/V2M clock support" if COMPILE_TEST
|
||||
select CLK_RZG2L
|
||||
@@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
|
||||
This is a driver for R-Car USB2 clock selector
|
||||
|
||||
config CLK_RZG2L
|
||||
bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
|
||||
bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST
|
||||
select RESET_CONTROLLER
|
||||
|
||||
config CLK_RZV2H
|
||||
|
||||
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A08G046) += r9a08g046-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
|
||||
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
|
||||
|
||||
@@ -1342,8 +1342,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
|
||||
/* Clear potentially pending resets */
|
||||
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
|
||||
clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
|
||||
/* Allow software reset */
|
||||
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
|
||||
/* Allow watchdog and software resets */
|
||||
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1 |
|
||||
R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
|
||||
clocks->reg + R9A06G032_SYSCTRL_RSTEN);
|
||||
|
||||
error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
|
||||
|
||||
@@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
|
||||
};
|
||||
|
||||
static const unsigned int r9a07g043_crit_resets[] = {
|
||||
R9A07G043_DMAC_ARESETN,
|
||||
R9A07G043_DMAC_RST_ASYNC,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARM64
|
||||
static const unsigned int r9a07g043_no_pm_mod_clks[] = {
|
||||
MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
|
||||
@@ -420,5 +425,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
|
||||
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
|
||||
#endif
|
||||
|
||||
/* Critical Resets */
|
||||
.crit_resets = r9a07g043_crit_resets,
|
||||
.num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),
|
||||
|
||||
.has_clk_mon_regs = true,
|
||||
};
|
||||
|
||||
@@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
|
||||
};
|
||||
|
||||
static const unsigned int r9a07g044_crit_resets[] = {
|
||||
R9A07G044_DMAC_ARESETN,
|
||||
R9A07G044_DMAC_RST_ASYNC,
|
||||
};
|
||||
|
||||
static const unsigned int r9a07g044_no_pm_mod_clks[] = {
|
||||
MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
|
||||
MOD_CLK_BASE + R9A07G044_CRU_VCLK,
|
||||
@@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
|
||||
.resets = r9a07g044_resets,
|
||||
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
|
||||
|
||||
/* Critical Resets */
|
||||
.crit_resets = r9a07g044_crit_resets,
|
||||
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
|
||||
|
||||
.has_clk_mon_regs = true,
|
||||
};
|
||||
#endif
|
||||
@@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
|
||||
.resets = r9a07g044_resets,
|
||||
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
|
||||
|
||||
/* Critical Resets */
|
||||
.crit_resets = r9a07g044_crit_resets,
|
||||
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
|
||||
|
||||
.has_clk_mon_regs = true,
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
|
||||
};
|
||||
|
||||
static const unsigned int r9a08g045_crit_resets[] = {
|
||||
R9A08G045_DMAC_ARESETN,
|
||||
R9A08G045_DMAC_RST_ASYNC,
|
||||
};
|
||||
|
||||
static const unsigned int r9a08g045_no_pm_mod_clks[] = {
|
||||
MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
|
||||
};
|
||||
@@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
|
||||
.resets = r9a08g045_resets,
|
||||
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
|
||||
|
||||
/* Critical Resets */
|
||||
.crit_resets = r9a08g045_crit_resets,
|
||||
.num_crit_resets = ARRAY_SIZE(r9a08g045_crit_resets),
|
||||
|
||||
.has_clk_mon_regs = true,
|
||||
};
|
||||
|
||||
153
drivers/clk/renesas/r9a08g046-cpg.c
Normal file
153
drivers/clk/renesas/r9a08g046-cpg.c
Normal file
@@ -0,0 +1,153 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* RZ/G3L CPG driver
|
||||
*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
|
||||
|
||||
#include "rzg2l-cpg.h"
|
||||
|
||||
/* RZ/G3L Specific registers. */
|
||||
#define G3L_CPG_PL2_DDIV (0x204)
|
||||
#define G3L_CPG_PL3_DDIV (0x208)
|
||||
#define G3L_CLKDIVSTATUS (0x280)
|
||||
|
||||
/* RZ/G3L Specific division configuration. */
|
||||
#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
|
||||
#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
|
||||
#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
|
||||
|
||||
/* RZ/G3L Clock status configuration. */
|
||||
#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
|
||||
#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
|
||||
#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_ETH0_TXC_TX_CLK_IN,
|
||||
CLK_ETH0_RXC_RX_CLK_IN,
|
||||
CLK_ETH1_TXC_TX_CLK_IN,
|
||||
CLK_ETH1_RXC_RX_CLK_IN,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_PLL2,
|
||||
CLK_PLL2_DIV2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL3_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
};
|
||||
|
||||
/* Divider tables */
|
||||
static const struct clk_div_table dtable_4_128[] = {
|
||||
{ 0, 4 },
|
||||
{ 1, 8 },
|
||||
{ 2, 16 },
|
||||
{ 3, 128 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_8_256[] = {
|
||||
{ 0, 8 },
|
||||
{ 1, 16 },
|
||||
{ 2, 32 },
|
||||
{ 3, 256 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN),
|
||||
DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN),
|
||||
DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN),
|
||||
DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
|
||||
|
||||
/* Core output clk */
|
||||
DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
|
||||
dtable_8_256, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
|
||||
dtable_4_128, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
|
||||
dtable_4_128, 0, 0, 0, NULL),
|
||||
};
|
||||
|
||||
static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
|
||||
DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, 0,
|
||||
MSTOP(BUS_PERI_COM, BIT(12))),
|
||||
DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0,
|
||||
MSTOP(BUS_PERI_CPU, BIT(13))),
|
||||
DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1,
|
||||
MSTOP(BUS_PERI_CPU, BIT(13))),
|
||||
DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0,
|
||||
MSTOP(BUS_REG1, BIT(2))),
|
||||
DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
|
||||
MSTOP(BUS_REG1, BIT(3))),
|
||||
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
|
||||
MSTOP(BUS_MCPU2, BIT(1))),
|
||||
};
|
||||
|
||||
static const struct rzg2l_reset r9a08g046_resets[] = {
|
||||
DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0),
|
||||
DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1),
|
||||
DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
|
||||
DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
|
||||
DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
|
||||
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
|
||||
};
|
||||
|
||||
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
|
||||
MOD_CLK_BASE + R9A08G046_IA55_CLK,
|
||||
MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
|
||||
};
|
||||
|
||||
static const unsigned int r9a08g046_crit_resets[] = {
|
||||
R9A08G046_DMAC_ARESETN,
|
||||
R9A08G046_DMAC_RST_ASYNC,
|
||||
};
|
||||
|
||||
const struct rzg2l_cpg_info r9a08g046_cpg_info = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r9a08g046_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r9a08g046_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r9a08g046_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r9a08g046_crit_mod_clks),
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r9a08g046_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
|
||||
.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a08g046_resets,
|
||||
.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */
|
||||
|
||||
/* Critical Resets */
|
||||
.crit_resets = r9a08g046_crit_resets,
|
||||
.num_crit_resets = ARRAY_SIZE(r9a08g046_crit_resets),
|
||||
|
||||
.has_clk_mon_regs = true,
|
||||
};
|
||||
@@ -224,6 +224,24 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
|
||||
BUS_MSTOP(11, BIT(3))),
|
||||
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
|
||||
@@ -424,6 +442,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(8, BIT(6))),
|
||||
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
|
||||
BUS_MSTOP(8, BIT(6))),
|
||||
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
|
||||
BUS_MSTOP(1, BIT(15))),
|
||||
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
|
||||
BUS_MSTOP(1, BIT(15))),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
|
||||
@@ -457,6 +479,12 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
|
||||
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
|
||||
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
|
||||
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
|
||||
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
|
||||
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
|
||||
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
|
||||
DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
|
||||
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
|
||||
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
|
||||
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
|
||||
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
|
||||
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
|
||||
@@ -503,6 +531,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
|
||||
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
|
||||
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
|
||||
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
|
||||
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
|
||||
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
|
||||
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
|
||||
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
|
||||
|
||||
@@ -273,22 +273,30 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(11, BIT(15))),
|
||||
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
|
||||
BUS_MSTOP(12, BIT(0))),
|
||||
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
|
||||
BUS_MSTOP(3, BIT(11) | BIT(12))),
|
||||
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
|
||||
BUS_MSTOP(11, BIT(3))),
|
||||
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
|
||||
@@ -389,24 +397,6 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(11, BIT(12))),
|
||||
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
|
||||
BUS_MSTOP(11, BIT(12))),
|
||||
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
|
||||
BUS_MSTOP(3, BIT(14))),
|
||||
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
|
||||
@@ -503,6 +493,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(8, BIT(6))),
|
||||
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
|
||||
BUS_MSTOP(8, BIT(6))),
|
||||
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
|
||||
BUS_MSTOP(1, BIT(15))),
|
||||
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
|
||||
BUS_MSTOP(1, BIT(15))),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
|
||||
@@ -569,10 +563,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
|
||||
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
|
||||
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
|
||||
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
|
||||
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
|
||||
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
|
||||
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
|
||||
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
|
||||
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
|
||||
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
|
||||
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
|
||||
@@ -593,6 +584,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
|
||||
DEF_RST(9, 2, 4, 3), /* RSCI8_TRESETN */
|
||||
DEF_RST(9, 3, 4, 4), /* RSCI9_PRESETN */
|
||||
DEF_RST(9, 4, 4, 5), /* RSCI9_TRESETN */
|
||||
DEF_RST(7, 9, 3, 10), /* RTC_0_RST_RTC */
|
||||
DEF_RST(7, 10, 3, 11), /* RTC_0_RST_RTC_V */
|
||||
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
|
||||
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
|
||||
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
|
||||
@@ -624,6 +617,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
|
||||
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
|
||||
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
|
||||
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
|
||||
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
|
||||
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
|
||||
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
|
||||
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
|
||||
|
||||
@@ -280,22 +280,30 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(11, BIT(15))),
|
||||
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
|
||||
BUS_MSTOP(12, BIT(0))),
|
||||
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
|
||||
BUS_MSTOP(3, BIT(10))),
|
||||
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
|
||||
BUS_MSTOP(1, BIT(0))),
|
||||
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
|
||||
BUS_MSTOP(5, BIT(12))),
|
||||
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
|
||||
BUS_MSTOP(5, BIT(13))),
|
||||
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
|
||||
BUS_MSTOP(3, BIT(11) | BIT(12))),
|
||||
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
|
||||
BUS_MSTOP(11, BIT(3))),
|
||||
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
|
||||
@@ -396,26 +404,6 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(11, BIT(12))),
|
||||
DEF_MOD("rsci9_ps_ps1_n", CLK_PLLCLN_DIV64, 8, 14, 4, 14,
|
||||
BUS_MSTOP(11, BIT(12))),
|
||||
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
|
||||
BUS_MSTOP(3, BIT(11) | BIT(12))),
|
||||
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
|
||||
BUS_MSTOP(11, BIT(0))),
|
||||
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
|
||||
BUS_MSTOP(11, BIT(1))),
|
||||
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
|
||||
BUS_MSTOP(11, BIT(2))),
|
||||
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
|
||||
BUS_MSTOP(3, BIT(14))),
|
||||
DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
|
||||
@@ -520,6 +508,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(8, BIT(6))),
|
||||
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
|
||||
BUS_MSTOP(8, BIT(6))),
|
||||
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
|
||||
BUS_MSTOP(1, BIT(13) | BIT(15))),
|
||||
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
|
||||
BUS_MSTOP(1, BIT(13) | BIT(15))),
|
||||
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
|
||||
@@ -598,10 +590,7 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
|
||||
DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
|
||||
DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
|
||||
DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
|
||||
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
|
||||
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
|
||||
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
|
||||
DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
|
||||
DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
|
||||
DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
|
||||
@@ -657,6 +646,7 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
|
||||
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
|
||||
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
|
||||
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
|
||||
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
|
||||
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
|
||||
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
|
||||
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
|
||||
|
||||
@@ -569,7 +569,7 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
|
||||
struct cpg_mssr_clk_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
unsigned int num_core_pm_clks;
|
||||
unsigned int core_pm_clks[];
|
||||
unsigned int core_pm_clks[] __counted_by(num_core_pm_clks);
|
||||
};
|
||||
|
||||
static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
|
||||
@@ -667,7 +667,7 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
||||
size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
|
||||
int ret;
|
||||
|
||||
pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
|
||||
pd = devm_kzalloc(dev, struct_size(pd, core_pm_clks, num_core_pm_clks), GFP_KERNEL);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
@@ -1439,7 +1439,8 @@ static int rzg2l_mod_clock_mstop_show(struct seq_file *s, void *what)
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(rzg2l_mod_clock_mstop);
|
||||
|
||||
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
static int rzg2l_mod_clock_endisable_helper(struct clk_hw *hw, bool enable,
|
||||
bool set_mstop_state)
|
||||
{
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
struct rzg2l_cpg_priv *priv = clock->priv;
|
||||
@@ -1464,9 +1465,11 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
|
||||
if (enable) {
|
||||
writel(value, priv->base + CLK_ON_R(reg));
|
||||
rzg2l_mod_clock_module_set_state(clock, false);
|
||||
if (set_mstop_state)
|
||||
rzg2l_mod_clock_module_set_state(clock, false);
|
||||
} else {
|
||||
rzg2l_mod_clock_module_set_state(clock, true);
|
||||
if (set_mstop_state)
|
||||
rzg2l_mod_clock_module_set_state(clock, true);
|
||||
writel(value, priv->base + CLK_ON_R(reg));
|
||||
}
|
||||
}
|
||||
@@ -1486,6 +1489,11 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
return error;
|
||||
}
|
||||
|
||||
static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
{
|
||||
return rzg2l_mod_clock_endisable_helper(hw, enable, true);
|
||||
}
|
||||
|
||||
static int rzg2l_mod_clock_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct mod_clock *clock = to_mod_clock(hw);
|
||||
@@ -1586,6 +1594,35 @@ static struct mstop *rzg2l_mod_clock_get_mstop(struct rzg2l_cpg_priv *priv, u32
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void rzg2l_mod_clock_init_mstop_helper(struct rzg2l_cpg_priv *priv,
|
||||
struct mod_clock *clk)
|
||||
{
|
||||
/*
|
||||
* Out of reset all modules are enabled. Set module state in case
|
||||
* associated clocks are disabled at probe/resume. Otherwise module
|
||||
* is in invalid HW state.
|
||||
*/
|
||||
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
|
||||
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
|
||||
rzg2l_mod_clock_module_set_state(clk, true);
|
||||
}
|
||||
}
|
||||
|
||||
static void rzg2l_mod_enable_crit_clock_init_mstop(struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct mod_clock *clk;
|
||||
struct clk_hw *hw;
|
||||
|
||||
for_each_mod_clock(clk, hw, priv) {
|
||||
if ((clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL) &&
|
||||
(!rzg2l_mod_clock_is_enabled(&clk->hw)))
|
||||
rzg2l_mod_clock_endisable_helper(&clk->hw, true, false);
|
||||
|
||||
if (clk->mstop)
|
||||
rzg2l_mod_clock_init_mstop_helper(priv, clk);
|
||||
}
|
||||
}
|
||||
|
||||
static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv)
|
||||
{
|
||||
struct mod_clock *clk;
|
||||
@@ -1595,15 +1632,7 @@ static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv)
|
||||
if (!clk->mstop)
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Out of reset all modules are enabled. Set module state
|
||||
* in case associated clocks are disabled at probe. Otherwise
|
||||
* module is in invalid HW state.
|
||||
*/
|
||||
scoped_guard(spinlock_irqsave, &priv->rmw_lock) {
|
||||
if (!rzg2l_mod_clock_is_enabled(&clk->hw))
|
||||
rzg2l_mod_clock_module_set_state(clk, true);
|
||||
}
|
||||
rzg2l_mod_clock_init_mstop_helper(priv, clk);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1765,6 +1794,13 @@ static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
|
||||
dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
|
||||
assert ? "assert" : "deassert", id, CLK_RST_R(reg));
|
||||
|
||||
if (assert) {
|
||||
for (unsigned int i = 0; i < priv->info->num_crit_resets; i++) {
|
||||
if (id == priv->info->crit_resets[i])
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (!assert)
|
||||
value |= mask;
|
||||
writel(value, priv->base + CLK_RST_R(reg));
|
||||
@@ -1802,6 +1838,20 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
|
||||
return __rzg2l_cpg_assert(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_deassert_crit_resets(struct reset_controller_dev *rcdev,
|
||||
const struct rzg2l_cpg_info *info)
|
||||
{
|
||||
int ret;
|
||||
|
||||
for (unsigned int i = 0; i < info->num_crit_resets; i++) {
|
||||
ret = rzg2l_cpg_deassert(rcdev, info->crit_resets[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
@@ -2051,6 +2101,10 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = rzg2l_cpg_deassert_crit_resets(&priv->rcdev, info);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fops);
|
||||
return 0;
|
||||
}
|
||||
@@ -2058,8 +2112,13 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
|
||||
static int rzg2l_cpg_resume(struct device *dev)
|
||||
{
|
||||
struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
rzg2l_mod_clock_init_mstop(priv);
|
||||
ret = rzg2l_cpg_deassert_crit_resets(&priv->rcdev, priv->info);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
rzg2l_mod_enable_crit_clock_init_mstop(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -2093,6 +2152,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
|
||||
.data = &r9a08g045_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A08G046
|
||||
{
|
||||
.compatible = "renesas,r9a08g046-cpg",
|
||||
.data = &r9a08g046_cpg_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R9A09G011
|
||||
{
|
||||
.compatible = "renesas,r9a09g011-cpg",
|
||||
|
||||
@@ -276,6 +276,9 @@ struct rzg2l_reset {
|
||||
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
|
||||
* should not be disabled without a knowledgeable driver
|
||||
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
|
||||
* @crit_resets: Array with Reset IDs of critical resets that should not be
|
||||
* asserted without a knowledgeable driver
|
||||
* @num_crit_resets: Number of entries in crit_resets[]
|
||||
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
|
||||
*/
|
||||
struct rzg2l_cpg_info {
|
||||
@@ -302,6 +305,10 @@ struct rzg2l_cpg_info {
|
||||
const unsigned int *crit_mod_clks;
|
||||
unsigned int num_crit_mod_clks;
|
||||
|
||||
/* Critical Resets that should not be asserted */
|
||||
const unsigned int *crit_resets;
|
||||
unsigned int num_crit_resets;
|
||||
|
||||
bool has_clk_mon_regs;
|
||||
};
|
||||
|
||||
@@ -309,6 +316,7 @@ extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a08g045_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a08g046_cpg_info;
|
||||
extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
|
||||
|
||||
int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);
|
||||
|
||||
12
include/dt-bindings/clock/econet,en751221-scu.h
Normal file
12
include/dt-bindings/clock/econet,en751221-scu.h
Normal file
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
|
||||
#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
|
||||
|
||||
#define EN751221_CLK_PCIE 0
|
||||
#define EN751221_CLK_SPI 1
|
||||
#define EN751221_CLK_BUS 2
|
||||
#define EN751221_CLK_CPU 3
|
||||
#define EN751221_CLK_GSW 4
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */
|
||||
285
include/dt-bindings/clock/eswin,eic7700-clock.h
Normal file
285
include/dt-bindings/clock/eswin,eic7700-clock.h
Normal file
@@ -0,0 +1,285 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
|
||||
* All rights reserved.
|
||||
*
|
||||
* Device Tree binding constants for EIC7700 clock controller.
|
||||
*
|
||||
* Authors:
|
||||
* Yifeng Huang <huangyifeng@eswincomputing.com>
|
||||
* Xuyang Dong <dongxuyang@eswincomputing.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
|
||||
#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
|
||||
|
||||
#define EIC7700_CLK_XTAL_32K 0
|
||||
#define EIC7700_CLK_PLL_CPU 1
|
||||
#define EIC7700_CLK_SPLL0_FOUT1 2
|
||||
#define EIC7700_CLK_SPLL0_FOUT2 3
|
||||
#define EIC7700_CLK_SPLL0_FOUT3 4
|
||||
#define EIC7700_CLK_SPLL1_FOUT1 5
|
||||
#define EIC7700_CLK_SPLL1_FOUT2 6
|
||||
#define EIC7700_CLK_SPLL1_FOUT3 7
|
||||
#define EIC7700_CLK_SPLL2_FOUT1 8
|
||||
#define EIC7700_CLK_SPLL2_FOUT2 9
|
||||
#define EIC7700_CLK_SPLL2_FOUT3 10
|
||||
#define EIC7700_CLK_VPLL_FOUT1 11
|
||||
#define EIC7700_CLK_VPLL_FOUT2 12
|
||||
#define EIC7700_CLK_VPLL_FOUT3 13
|
||||
#define EIC7700_CLK_APLL_FOUT1 14
|
||||
#define EIC7700_CLK_APLL_FOUT2 15
|
||||
#define EIC7700_CLK_APLL_FOUT3 16
|
||||
#define EIC7700_CLK_EXT_MCLK 17
|
||||
#define EIC7700_CLK_LPDDR_REF_BAK 18
|
||||
#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19
|
||||
#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20
|
||||
#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21
|
||||
#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22
|
||||
#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23
|
||||
#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24
|
||||
#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25
|
||||
#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26
|
||||
#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27
|
||||
#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28
|
||||
#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29
|
||||
#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30
|
||||
#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31
|
||||
#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32
|
||||
#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33
|
||||
#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34
|
||||
#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35
|
||||
#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36
|
||||
#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37
|
||||
#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38
|
||||
#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39
|
||||
#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40
|
||||
#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41
|
||||
#define EIC7700_CLK_MUX_RMII_REF_2MUX 42
|
||||
#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43
|
||||
#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44
|
||||
#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45
|
||||
#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46
|
||||
#define EIC7700_CLK_DIV_SYS_CFG_DYNM 47
|
||||
#define EIC7700_CLK_DIV_NOC_NSP_DYNM 48
|
||||
#define EIC7700_CLK_DIV_BOOTSPI_DYNM 49
|
||||
#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50
|
||||
#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51
|
||||
#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52
|
||||
#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53
|
||||
#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54
|
||||
#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55
|
||||
#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56
|
||||
#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57
|
||||
#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58
|
||||
#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59
|
||||
#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60
|
||||
#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61
|
||||
#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62
|
||||
#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63
|
||||
#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64
|
||||
#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65
|
||||
#define EIC7700_CLK_DIV_VI_ACLK_DYNM 66
|
||||
#define EIC7700_CLK_DIV_VI_DVP_DYNM 67
|
||||
#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68
|
||||
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69
|
||||
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70
|
||||
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71
|
||||
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72
|
||||
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73
|
||||
#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74
|
||||
#define EIC7700_CLK_DIV_VO_ACLK_DYNM 75
|
||||
#define EIC7700_CLK_DIV_IESMCLK_DYNM 76
|
||||
#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77
|
||||
#define EIC7700_CLK_DIV_VO_MCLK_DYNM 78
|
||||
#define EIC7700_CLK_DIV_VC_ACLK_DYNM 79
|
||||
#define EIC7700_CLK_DIV_JD_DYNM 80
|
||||
#define EIC7700_CLK_DIV_JE_DYNM 81
|
||||
#define EIC7700_CLK_DIV_VE_DYNM 82
|
||||
#define EIC7700_CLK_DIV_VD_DYNM 83
|
||||
#define EIC7700_CLK_DIV_G2D_DYNM 84
|
||||
#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85
|
||||
#define EIC7700_CLK_DIV_CRYPTO_DYNM 86
|
||||
#define EIC7700_CLK_DIV_VI_DW_DYNM 87
|
||||
#define EIC7700_CLK_DIV_NPU_E31_DYNM 88
|
||||
#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89
|
||||
#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90
|
||||
#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91
|
||||
#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92
|
||||
#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93
|
||||
#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94
|
||||
#define EIC7700_CLK_DIV_AON_RTC_DYNM 95
|
||||
#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96
|
||||
#define EIC7700_CLK_DIV_VO_CEC_DYNM 97
|
||||
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98
|
||||
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99
|
||||
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100
|
||||
#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101
|
||||
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102
|
||||
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103
|
||||
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104
|
||||
#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105
|
||||
#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106
|
||||
#define EIC7700_CLK_GATE_SPLL0_FOUT2 107
|
||||
#define EIC7700_CLK_GATE_NOC_NSP_CLK 108
|
||||
#define EIC7700_CLK_GATE_BOOTSPI 109
|
||||
#define EIC7700_CLK_GATE_BOOTSPI_CFG 110
|
||||
#define EIC7700_CLK_GATE_SCPU_CORE 111
|
||||
#define EIC7700_CLK_GATE_SCPU_BUS 112
|
||||
#define EIC7700_CLK_GATE_LPCPU_CORE 113
|
||||
#define EIC7700_CLK_GATE_LPCPU_BUS 114
|
||||
#define EIC7700_CLK_GATE_GPU_ACLK 115
|
||||
#define EIC7700_CLK_GATE_GPU_GRAY_CLK 116
|
||||
#define EIC7700_CLK_GATE_GPU_CFG_CLK 117
|
||||
#define EIC7700_CLK_GATE_DSPT_ACLK 118
|
||||
#define EIC7700_CLK_GATE_DSPT_CFG_CLK 119
|
||||
#define EIC7700_CLK_GATE_D2D_ACLK 120
|
||||
#define EIC7700_CLK_GATE_D2D_CFG_CLK 121
|
||||
#define EIC7700_CLK_GATE_TCU_ACLK 122
|
||||
#define EIC7700_CLK_GATE_TCU_CFG_CLK 123
|
||||
#define EIC7700_CLK_GATE_DDRT_CFG_CLK 124
|
||||
#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125
|
||||
#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126
|
||||
#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127
|
||||
#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128
|
||||
#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129
|
||||
#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130
|
||||
#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131
|
||||
#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132
|
||||
#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133
|
||||
#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134
|
||||
#define EIC7700_CLK_GATE_TIMER_CLK_0 135
|
||||
#define EIC7700_CLK_GATE_TIMER_CLK_1 136
|
||||
#define EIC7700_CLK_GATE_TIMER_CLK_2 137
|
||||
#define EIC7700_CLK_GATE_TIMER_CLK_3 138
|
||||
#define EIC7700_CLK_GATE_TIMER_PCLK_0 139
|
||||
#define EIC7700_CLK_GATE_TIMER_PCLK_1 140
|
||||
#define EIC7700_CLK_GATE_TIMER_PCLK_2 141
|
||||
#define EIC7700_CLK_GATE_TIMER_PCLK_3 142
|
||||
#define EIC7700_CLK_GATE_TIMER3_CLK8 143
|
||||
#define EIC7700_CLK_GATE_PCIET_ACLK 144
|
||||
#define EIC7700_CLK_GATE_PCIET_CFG_CLK 145
|
||||
#define EIC7700_CLK_GATE_PCIET_CR_CLK 146
|
||||
#define EIC7700_CLK_GATE_PCIET_AUX_CLK 147
|
||||
#define EIC7700_CLK_GATE_NPU_ACLK 148
|
||||
#define EIC7700_CLK_GATE_NPU_CFG_CLK 149
|
||||
#define EIC7700_CLK_GATE_NPU_LLC_ACLK 150
|
||||
#define EIC7700_CLK_GATE_NPU_CLK 151
|
||||
#define EIC7700_CLK_GATE_NPU_E31_CLK 152
|
||||
#define EIC7700_CLK_GATE_VI_ACLK 153
|
||||
#define EIC7700_CLK_GATE_VI_DVP_CLK 154
|
||||
#define EIC7700_CLK_GATE_VI_CFG_CLK 155
|
||||
#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156
|
||||
#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157
|
||||
#define EIC7700_CLK_GATE_VI_SHUTTER_0 158
|
||||
#define EIC7700_CLK_GATE_VI_SHUTTER_1 159
|
||||
#define EIC7700_CLK_GATE_VI_SHUTTER_2 160
|
||||
#define EIC7700_CLK_GATE_VI_SHUTTER_3 161
|
||||
#define EIC7700_CLK_GATE_VI_SHUTTER_4 162
|
||||
#define EIC7700_CLK_GATE_VI_SHUTTER_5 163
|
||||
#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164
|
||||
#define EIC7700_CLK_GATE_VI_PHY_CFG 165
|
||||
#define EIC7700_CLK_GATE_VO_ACLK 166
|
||||
#define EIC7700_CLK_GATE_VO_CFG_CLK 167
|
||||
#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168
|
||||
#define EIC7700_CLK_GATE_VO_PIXEL_CLK 169
|
||||
#define EIC7700_CLK_GATE_VO_I2S_MCLK 170
|
||||
#define EIC7700_CLK_GATE_HSP_CFG_CLK 171
|
||||
#define EIC7700_CLK_GATE_VC_ACLK 172
|
||||
#define EIC7700_CLK_GATE_VC_CFG_CLK 173
|
||||
#define EIC7700_CLK_GATE_VC_JE_CLK 174
|
||||
#define EIC7700_CLK_GATE_VC_JD_CLK 175
|
||||
#define EIC7700_CLK_GATE_VC_VE_CLK 176
|
||||
#define EIC7700_CLK_GATE_VC_VD_CLK 177
|
||||
#define EIC7700_CLK_GATE_G2D_CFG_CLK 178
|
||||
#define EIC7700_CLK_GATE_G2D_CLK 179
|
||||
#define EIC7700_CLK_GATE_G2D_ACLK 180
|
||||
#define EIC7700_CLK_GATE_AONDMA_CFG 181
|
||||
#define EIC7700_CLK_GATE_AONDMA_ACLK 182
|
||||
#define EIC7700_CLK_GATE_AON_ACLK 183
|
||||
#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184
|
||||
#define EIC7700_CLK_GATE_VO_CR_CLK 185
|
||||
#define EIC7700_CLK_GATE_HSP_ACLK 186
|
||||
#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187
|
||||
#define EIC7700_CLK_GATE_RTC_CFG 188
|
||||
#define EIC7700_CLK_GATE_RTC 189
|
||||
#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190
|
||||
#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191
|
||||
#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192
|
||||
#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193
|
||||
#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194
|
||||
#define EIC7700_CLK_GATE_HSP_RMII_REF_0 195
|
||||
#define EIC7700_CLK_GATE_HSP_RMII_REF_1 196
|
||||
#define EIC7700_CLK_GATE_PKA_CFG 197
|
||||
#define EIC7700_CLK_GATE_SPACC_CFG 198
|
||||
#define EIC7700_CLK_GATE_CRYPTO 199
|
||||
#define EIC7700_CLK_GATE_TRNG_CFG 200
|
||||
#define EIC7700_CLK_GATE_OTP_CFG 201
|
||||
#define EIC7700_CLK_GATE_MAILBOX_0 202
|
||||
#define EIC7700_CLK_GATE_MAILBOX_1 203
|
||||
#define EIC7700_CLK_GATE_MAILBOX_2 204
|
||||
#define EIC7700_CLK_GATE_MAILBOX_3 205
|
||||
#define EIC7700_CLK_GATE_MAILBOX_4 206
|
||||
#define EIC7700_CLK_GATE_MAILBOX_5 207
|
||||
#define EIC7700_CLK_GATE_MAILBOX_6 208
|
||||
#define EIC7700_CLK_GATE_MAILBOX_7 209
|
||||
#define EIC7700_CLK_GATE_MAILBOX_8 210
|
||||
#define EIC7700_CLK_GATE_MAILBOX_9 211
|
||||
#define EIC7700_CLK_GATE_MAILBOX_10 212
|
||||
#define EIC7700_CLK_GATE_MAILBOX_11 213
|
||||
#define EIC7700_CLK_GATE_MAILBOX_12 214
|
||||
#define EIC7700_CLK_GATE_MAILBOX_13 215
|
||||
#define EIC7700_CLK_GATE_MAILBOX_14 216
|
||||
#define EIC7700_CLK_GATE_MAILBOX_15 217
|
||||
#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218
|
||||
#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219
|
||||
#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220
|
||||
#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221
|
||||
#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222
|
||||
#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223
|
||||
#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224
|
||||
#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225
|
||||
#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226
|
||||
#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227
|
||||
#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228
|
||||
#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229
|
||||
#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230
|
||||
#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231
|
||||
#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232
|
||||
#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233
|
||||
#define EIC7700_CLK_GATE_LSP_PVT_PCLK 234
|
||||
#define EIC7700_CLK_GATE_AON_I2C0_PCLK 235
|
||||
#define EIC7700_CLK_GATE_AON_I2C1_PCLK 236
|
||||
#define EIC7700_CLK_GATE_LSP_UART0_PCLK 237
|
||||
#define EIC7700_CLK_GATE_LSP_UART1_PCLK 238
|
||||
#define EIC7700_CLK_GATE_LSP_UART2_PCLK 239
|
||||
#define EIC7700_CLK_GATE_LSP_UART3_PCLK 240
|
||||
#define EIC7700_CLK_GATE_LSP_UART4_PCLK 241
|
||||
#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242
|
||||
#define EIC7700_CLK_GATE_LSP_FAN_PCLK 243
|
||||
#define EIC7700_CLK_GATE_LSP_PVT0_CLK 244
|
||||
#define EIC7700_CLK_GATE_LSP_PVT1_CLK 245
|
||||
#define EIC7700_CLK_GATE_VC_JE_PCLK 246
|
||||
#define EIC7700_CLK_GATE_VC_JD_PCLK 247
|
||||
#define EIC7700_CLK_GATE_VC_VE_PCLK 248
|
||||
#define EIC7700_CLK_GATE_VC_VD_PCLK 249
|
||||
#define EIC7700_CLK_GATE_VC_MON_PCLK 250
|
||||
#define EIC7700_CLK_GATE_HSP_DMA0_CLK 251
|
||||
#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252
|
||||
#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253
|
||||
#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254
|
||||
#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255
|
||||
#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256
|
||||
#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257
|
||||
#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258
|
||||
#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259
|
||||
#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260
|
||||
#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261
|
||||
#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262
|
||||
#define EIC7700_CLK_DIV_NOC_WDREF_DYNM 263
|
||||
#define EIC7700_CLK_GATE_DDR0_TRACE 264
|
||||
#define EIC7700_CLK_GATE_DDR1_TRACE 265
|
||||
#define EIC7700_CLK_GATE_RNOC_NSP 266
|
||||
#define EIC7700_CLK_GATE_NOC_WDREF 267
|
||||
|
||||
#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */
|
||||
342
include/dt-bindings/clock/renesas,r9a08g046-cpg.h
Normal file
342
include/dt-bindings/clock/renesas,r9a08g046-cpg.h
Normal file
@@ -0,0 +1,342 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
*
|
||||
* Copyright (C) 2026 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R9A08G046 CPG Core Clocks */
|
||||
#define R9A08G046_CLK_I 0
|
||||
#define R9A08G046_CLK_IC0 1
|
||||
#define R9A08G046_CLK_IC1 2
|
||||
#define R9A08G046_CLK_IC2 3
|
||||
#define R9A08G046_CLK_IC3 4
|
||||
#define R9A08G046_CLK_P0 5
|
||||
#define R9A08G046_CLK_P1 6
|
||||
#define R9A08G046_CLK_P2 7
|
||||
#define R9A08G046_CLK_P3 8
|
||||
#define R9A08G046_CLK_P4 9
|
||||
#define R9A08G046_CLK_P5 10
|
||||
#define R9A08G046_CLK_P6 11
|
||||
#define R9A08G046_CLK_P7 12
|
||||
#define R9A08G046_CLK_P8 13
|
||||
#define R9A08G046_CLK_P9 14
|
||||
#define R9A08G046_CLK_P10 15
|
||||
#define R9A08G046_CLK_P13 16
|
||||
#define R9A08G046_CLK_P14 17
|
||||
#define R9A08G046_CLK_P15 18
|
||||
#define R9A08G046_CLK_P16 19
|
||||
#define R9A08G046_CLK_P17 20
|
||||
#define R9A08G046_CLK_P18 21
|
||||
#define R9A08G046_CLK_P19 22
|
||||
#define R9A08G046_CLK_P20 23
|
||||
#define R9A08G046_CLK_M0 24
|
||||
#define R9A08G046_CLK_M1 25
|
||||
#define R9A08G046_CLK_M2 26
|
||||
#define R9A08G046_CLK_M3 27
|
||||
#define R9A08G046_CLK_M4 28
|
||||
#define R9A08G046_CLK_M5 29
|
||||
#define R9A08G046_CLK_M6 30
|
||||
#define R9A08G046_CLK_AT 31
|
||||
#define R9A08G046_CLK_B 32
|
||||
#define R9A08G046_CLK_ETHTX01 33
|
||||
#define R9A08G046_CLK_ETHTX02 34
|
||||
#define R9A08G046_CLK_ETHRX01 35
|
||||
#define R9A08G046_CLK_ETHRX02 36
|
||||
#define R9A08G046_CLK_ETHRM0 37
|
||||
#define R9A08G046_CLK_ETHTX11 38
|
||||
#define R9A08G046_CLK_ETHTX12 39
|
||||
#define R9A08G046_CLK_ETHRX11 40
|
||||
#define R9A08G046_CLK_ETHRX12 41
|
||||
#define R9A08G046_CLK_ETHRM1 42
|
||||
#define R9A08G046_CLK_G 43
|
||||
#define R9A08G046_CLK_HP 44
|
||||
#define R9A08G046_CLK_SD0 45
|
||||
#define R9A08G046_CLK_SD1 46
|
||||
#define R9A08G046_CLK_SD2 47
|
||||
#define R9A08G046_CLK_SPI0 48
|
||||
#define R9A08G046_CLK_SPI1 49
|
||||
#define R9A08G046_CLK_S0 50
|
||||
#define R9A08G046_CLK_SWD 51
|
||||
#define R9A08G046_OSCCLK 52
|
||||
#define R9A08G046_OSCCLK2 53
|
||||
#define R9A08G046_MIPI_DSI_PLLCLK 54
|
||||
#define R9A08G046_USB_SCLK 55
|
||||
|
||||
/* R9A08G046 Module Clocks */
|
||||
#define R9A08G046_CA55_SCLK 0
|
||||
#define R9A08G046_CA55_PCLK 1
|
||||
#define R9A08G046_CA55_ATCLK 2
|
||||
#define R9A08G046_CA55_GICCLK 3
|
||||
#define R9A08G046_CA55_PERICLK 4
|
||||
#define R9A08G046_CA55_ACLK 5
|
||||
#define R9A08G046_CA55_TSCLK 6
|
||||
#define R9A08G046_CA55_CORECLK0 7
|
||||
#define R9A08G046_CA55_CORECLK1 8
|
||||
#define R9A08G046_CA55_CORECLK2 9
|
||||
#define R9A08G046_CA55_CORECLK3 10
|
||||
#define R9A08G046_SRAM_ACPU_ACLK0 11
|
||||
#define R9A08G046_SRAM_ACPU_ACLK1 12
|
||||
#define R9A08G046_SRAM_ACPU_ACLK2 13
|
||||
#define R9A08G046_GIC600_GICCLK 14
|
||||
#define R9A08G046_IA55_CLK 15
|
||||
#define R9A08G046_IA55_PCLK 16
|
||||
#define R9A08G046_MHU_PCLK 17
|
||||
#define R9A08G046_SYC_CNT_CLK 18
|
||||
#define R9A08G046_DMAC_ACLK 19
|
||||
#define R9A08G046_DMAC_PCLK 20
|
||||
#define R9A08G046_OSTM0_PCLK 21
|
||||
#define R9A08G046_OSTM1_PCLK 22
|
||||
#define R9A08G046_OSTM2_PCLK 23
|
||||
#define R9A08G046_MTU_X_MCK_MTU3 24
|
||||
#define R9A08G046_POE3_CLKM_POE 25
|
||||
#define R9A08G046_GPT_PCLK 26
|
||||
#define R9A08G046_POEG_A_CLKP 27
|
||||
#define R9A08G046_POEG_B_CLKP 28
|
||||
#define R9A08G046_POEG_C_CLKP 29
|
||||
#define R9A08G046_POEG_D_CLKP 30
|
||||
#define R9A08G046_WDT0_PCLK 31
|
||||
#define R9A08G046_WDT0_CLK 32
|
||||
#define R9A08G046_WDT1_PCLK 33
|
||||
#define R9A08G046_WDT1_CLK 34
|
||||
#define R9A08G046_WDT2_PCLK 35
|
||||
#define R9A08G046_WDT2_CLK 36
|
||||
#define R9A08G046_XSPI_HCLK 37
|
||||
#define R9A08G046_XSPI_ACLK 38
|
||||
#define R9A08G046_XSPI_CLK 39
|
||||
#define R9A08G046_XSPI_CLKX2 40
|
||||
#define R9A08G046_SDHI0_IMCLK 41
|
||||
#define R9A08G046_SDHI0_IMCLK2 42
|
||||
#define R9A08G046_SDHI0_CLK_HS 43
|
||||
#define R9A08G046_SDHI0_IACLKS 44
|
||||
#define R9A08G046_SDHI0_IACLKM 45
|
||||
#define R9A08G046_SDHI1_IMCLK 46
|
||||
#define R9A08G046_SDHI1_IMCLK2 47
|
||||
#define R9A08G046_SDHI1_CLK_HS 48
|
||||
#define R9A08G046_SDHI1_IACLKS 49
|
||||
#define R9A08G046_SDHI1_IACLKM 50
|
||||
#define R9A08G046_SDHI2_IMCLK 51
|
||||
#define R9A08G046_SDHI2_IMCLK2 52
|
||||
#define R9A08G046_SDHI2_CLK_HS 53
|
||||
#define R9A08G046_SDHI2_IACLKS 54
|
||||
#define R9A08G046_SDHI2_IACLKM 55
|
||||
#define R9A08G046_GE3D_CLK 56
|
||||
#define R9A08G046_GE3D_AXI_CLK 57
|
||||
#define R9A08G046_GE3D_ACE_CLK 58
|
||||
#define R9A08G046_ISU_ACLK 59
|
||||
#define R9A08G046_ISU_PCLK 60
|
||||
#define R9A08G046_H264_CLK_A 61
|
||||
#define R9A08G046_H264_CLK_P 62
|
||||
#define R9A08G046_CRU_SYSCLK 63
|
||||
#define R9A08G046_CRU_VCLK 64
|
||||
#define R9A08G046_CRU_PCLK 65
|
||||
#define R9A08G046_CRU_ACLK 66
|
||||
#define R9A08G046_MIPI_DSI_SYSCLK 67
|
||||
#define R9A08G046_MIPI_DSI_ACLK 68
|
||||
#define R9A08G046_MIPI_DSI_PCLK 69
|
||||
#define R9A08G046_MIPI_DSI_VCLK 70
|
||||
#define R9A08G046_MIPI_DSI_LPCLK 71
|
||||
#define R9A08G046_LVDS_PLLCLK 72
|
||||
#define R9A08G046_LVDS_CLK_DOT0 73
|
||||
#define R9A08G046_LCDC_CLK_A 74
|
||||
#define R9A08G046_LCDC_CLK_D 75
|
||||
#define R9A08G046_LCDC_CLK_P 76
|
||||
#define R9A08G046_SSI0_PCLK2 77
|
||||
#define R9A08G046_SSI0_PCLK_SFR 78
|
||||
#define R9A08G046_SSI1_PCLK2 79
|
||||
#define R9A08G046_SSI1_PCLK_SFR 80
|
||||
#define R9A08G046_SSI2_PCLK2 81
|
||||
#define R9A08G046_SSI2_PCLK_SFR 82
|
||||
#define R9A08G046_SSI3_PCLK2 83
|
||||
#define R9A08G046_SSI3_PCLK_SFR 84
|
||||
#define R9A08G046_USB_U2H0_HCLK 85
|
||||
#define R9A08G046_USB_U2H1_HCLK 86
|
||||
#define R9A08G046_USB_U2P0_EXR_CPUCLK 87
|
||||
#define R9A08G046_USB_U2P1_EXR_CPUCLK 88
|
||||
#define R9A08G046_USB_PCLK 89
|
||||
#define R9A08G046_ETH0_CLK_AXI 90
|
||||
#define R9A08G046_ETH0_CLK_CHI 91
|
||||
#define R9A08G046_ETH0_CLK_TX_I 92
|
||||
#define R9A08G046_ETH0_CLK_RX_I 93
|
||||
#define R9A08G046_ETH0_CLK_TX_180_I 94
|
||||
#define R9A08G046_ETH0_CLK_RX_180_I 95
|
||||
#define R9A08G046_ETH0_CLK_RMII_I 96
|
||||
#define R9A08G046_ETH0_CLK_PTP_REF_I 97
|
||||
#define R9A08G046_ETH0_CLK_TX_I_RMII 98
|
||||
#define R9A08G046_ETH0_CLK_RX_I_RMII 99
|
||||
#define R9A08G046_ETH1_CLK_AXI 100
|
||||
#define R9A08G046_ETH1_CLK_CHI 101
|
||||
#define R9A08G046_ETH1_CLK_TX_I 102
|
||||
#define R9A08G046_ETH1_CLK_RX_I 103
|
||||
#define R9A08G046_ETH1_CLK_TX_180_I 104
|
||||
#define R9A08G046_ETH1_CLK_RX_180_I 105
|
||||
#define R9A08G046_ETH1_CLK_RMII_I 106
|
||||
#define R9A08G046_ETH1_CLK_PTP_REF_I 107
|
||||
#define R9A08G046_ETH1_CLK_TX_I_RMII 108
|
||||
#define R9A08G046_ETH1_CLK_RX_I_RMII 109
|
||||
#define R9A08G046_I2C0_PCLK 110
|
||||
#define R9A08G046_I2C1_PCLK 111
|
||||
#define R9A08G046_I2C2_PCLK 112
|
||||
#define R9A08G046_I2C3_PCLK 113
|
||||
#define R9A08G046_SCIF0_CLK_PCK 114
|
||||
#define R9A08G046_SCIF1_CLK_PCK 115
|
||||
#define R9A08G046_SCIF2_CLK_PCK 116
|
||||
#define R9A08G046_SCIF3_CLK_PCK 117
|
||||
#define R9A08G046_SCIF4_CLK_PCK 118
|
||||
#define R9A08G046_SCIF5_CLK_PCK 119
|
||||
#define R9A08G046_RSCI0_PCLK 120
|
||||
#define R9A08G046_RSCI0_TCLK 121
|
||||
#define R9A08G046_RSCI1_PCLK 122
|
||||
#define R9A08G046_RSCI1_TCLK 123
|
||||
#define R9A08G046_RSCI2_PCLK 124
|
||||
#define R9A08G046_RSCI2_TCLK 125
|
||||
#define R9A08G046_RSCI3_PCLK 126
|
||||
#define R9A08G046_RSCI3_TCLK 127
|
||||
#define R9A08G046_RSPI0_PCLK 128
|
||||
#define R9A08G046_RSPI0_TCLK 129
|
||||
#define R9A08G046_RSPI1_PCLK 130
|
||||
#define R9A08G046_RSPI1_TCLK 131
|
||||
#define R9A08G046_RSPI2_PCLK 132
|
||||
#define R9A08G046_RSPI2_TCLK 133
|
||||
#define R9A08G046_CANFD_PCLK 134
|
||||
#define R9A08G046_CANFD_CLK_RAM 135
|
||||
#define R9A08G046_GPIO_HCLK 136
|
||||
#define R9A08G046_ADC0_ADCLK 137
|
||||
#define R9A08G046_ADC0_PCLK 138
|
||||
#define R9A08G046_ADC1_ADCLK 139
|
||||
#define R9A08G046_ADC1_PCLK 140
|
||||
#define R9A08G046_TSU_PCLK 141
|
||||
#define R9A08G046_PDM_PCLK 142
|
||||
#define R9A08G046_PDM_CCLK 143
|
||||
#define R9A08G046_PCI_ACLK 144
|
||||
#define R9A08G046_PCI_CLKL1PM 145
|
||||
#define R9A08G046_PCI_CLK_PMU 146
|
||||
#define R9A08G046_SPDIF_PCLK 147
|
||||
#define R9A08G046_I3C_TCLK 148
|
||||
#define R9A08G046_I3C_PCLK 149
|
||||
#define R9A08G046_VBAT_BCLK 150
|
||||
#define R9A08G046_BSC_X_BCK_BSC 151
|
||||
|
||||
/* R9A08G046 Resets */
|
||||
#define R9A08G046_CA55_RST0_0 0
|
||||
#define R9A08G046_CA55_RST0_1 1
|
||||
#define R9A08G046_CA55_RST0_2 2
|
||||
#define R9A08G046_CA55_RST0_3 3
|
||||
#define R9A08G046_CA55_RST4_0 4
|
||||
#define R9A08G046_CA55_RST4_1 5
|
||||
#define R9A08G046_CA55_RST4_2 6
|
||||
#define R9A08G046_CA55_RST4_3 7
|
||||
#define R9A08G046_CA55_RST8 8
|
||||
#define R9A08G046_CA55_RST9 9
|
||||
#define R9A08G046_CA55_RST10 10
|
||||
#define R9A08G046_CA55_RST11 11
|
||||
#define R9A08G046_CA55_RST12 12
|
||||
#define R9A08G046_CA55_RST13 13
|
||||
#define R9A08G046_CA55_RST14 14
|
||||
#define R9A08G046_CA55_RST15 15
|
||||
#define R9A08G046_CA55_RST16 16
|
||||
#define R9A08G046_SRAM_ACPU_ARESETN0 17
|
||||
#define R9A08G046_SRAM_ACPU_ARESETN1 18
|
||||
#define R9A08G046_SRAM_ACPU_ARESETN2 19
|
||||
#define R9A08G046_GIC600_GICRESET_N 20
|
||||
#define R9A08G046_GIC600_DBG_GICRESET_N 21
|
||||
#define R9A08G046_IA55_RESETN 22
|
||||
#define R9A08G046_MHU_RESETN 23
|
||||
#define R9A08G046_SYC_RESETN 24
|
||||
#define R9A08G046_DMAC_ARESETN 25
|
||||
#define R9A08G046_DMAC_RST_ASYNC 26
|
||||
#define R9A08G046_GTM0_PRESETZ 27
|
||||
#define R9A08G046_GTM1_PRESETZ 28
|
||||
#define R9A08G046_GTM2_PRESETZ 29
|
||||
#define R9A08G046_MTU_X_PRESET_MTU3 30
|
||||
#define R9A08G046_POE3_RST_M_REG 31
|
||||
#define R9A08G046_GPT_RST_C 32
|
||||
#define R9A08G046_POEG_A_RST 33
|
||||
#define R9A08G046_POEG_B_RST 34
|
||||
#define R9A08G046_POEG_C_RST 35
|
||||
#define R9A08G046_POEG_D_RST 36
|
||||
#define R9A08G046_WDT0_PRESETN 37
|
||||
#define R9A08G046_WDT1_PRESETN 38
|
||||
#define R9A08G046_WDT2_PRESETN 39
|
||||
#define R9A08G046_XSPI_HRESETN 40
|
||||
#define R9A08G046_XSPI_ARESETN 41
|
||||
#define R9A08G046_SDHI0_IXRST 42
|
||||
#define R9A08G046_SDHI1_IXRST 43
|
||||
#define R9A08G046_SDHI2_IXRST 44
|
||||
#define R9A08G046_SDHI0_IXRSTAXIM 45
|
||||
#define R9A08G046_SDHI0_IXRSTAXIS 46
|
||||
#define R9A08G046_SDHI1_IXRSTAXIM 47
|
||||
#define R9A08G046_SDHI1_IXRSTAXIS 48
|
||||
#define R9A08G046_SDHI2_IXRSTAXIM 49
|
||||
#define R9A08G046_SDHI2_IXRSTAXIS 50
|
||||
#define R9A08G046_GE3D_RESETN 51
|
||||
#define R9A08G046_GE3D_AXI_RESETN 52
|
||||
#define R9A08G046_GE3D_ACE_RESETN 53
|
||||
#define R9A08G046_ISU_ARESETN 54
|
||||
#define R9A08G046_ISU_PRESETN 55
|
||||
#define R9A08G046_H264_X_RESET_VCP 56
|
||||
#define R9A08G046_H264_CP_PRESET_P 57
|
||||
#define R9A08G046_CRU_CMN_RSTB 58
|
||||
#define R9A08G046_CRU_PRESETN 59
|
||||
#define R9A08G046_CRU_ARESETN 60
|
||||
#define R9A08G046_MIPI_DSI_CMN_RSTB 61
|
||||
#define R9A08G046_MIPI_DSI_ARESET_N 62
|
||||
#define R9A08G046_MIPI_DSI_PRESET_N 63
|
||||
#define R9A08G046_LCDC_RESET_N 64
|
||||
#define R9A08G046_SSI0_RST_M2_REG 65
|
||||
#define R9A08G046_SSI1_RST_M2_REG 66
|
||||
#define R9A08G046_SSI2_RST_M2_REG 67
|
||||
#define R9A08G046_SSI3_RST_M2_REG 68
|
||||
#define R9A08G046_USB_U2H0_HRESETN 69
|
||||
#define R9A08G046_USB_U2H1_HRESETN 70
|
||||
#define R9A08G046_USB_U2P0_EXL_SYSRST 71
|
||||
#define R9A08G046_USB_PRESETN 72
|
||||
#define R9A08G046_USB_U2P1_EXL_SYSRST 73
|
||||
#define R9A08G046_ETH0_ARESET_N 74
|
||||
#define R9A08G046_ETH1_ARESET_N 75
|
||||
#define R9A08G046_I2C0_MRST 76
|
||||
#define R9A08G046_I2C1_MRST 77
|
||||
#define R9A08G046_I2C2_MRST 78
|
||||
#define R9A08G046_I2C3_MRST 79
|
||||
#define R9A08G046_SCIF0_RST_SYSTEM_N 80
|
||||
#define R9A08G046_SCIF1_RST_SYSTEM_N 81
|
||||
#define R9A08G046_SCIF2_RST_SYSTEM_N 82
|
||||
#define R9A08G046_SCIF3_RST_SYSTEM_N 83
|
||||
#define R9A08G046_SCIF4_RST_SYSTEM_N 84
|
||||
#define R9A08G046_SCIF5_RST_SYSTEM_N 85
|
||||
#define R9A08G046_RSPI0_PRESETN 86
|
||||
#define R9A08G046_RSPI1_PRESETN 87
|
||||
#define R9A08G046_RSPI2_PRESETN 88
|
||||
#define R9A08G046_RSPI0_TRESETN 89
|
||||
#define R9A08G046_RSPI1_TRESETN 90
|
||||
#define R9A08G046_RSPI2_TRESETN 91
|
||||
#define R9A08G046_CANFD_RSTP_N 92
|
||||
#define R9A08G046_CANFD_RSTC_N 93
|
||||
#define R9A08G046_GPIO_RSTN 94
|
||||
#define R9A08G046_GPIO_PORT_RESETN 95
|
||||
#define R9A08G046_GPIO_SPARE_RESETN 96
|
||||
#define R9A08G046_ADC0_PRESETN 97
|
||||
#define R9A08G046_ADC0_ADRST_N 98
|
||||
#define R9A08G046_ADC1_PRESETN 99
|
||||
#define R9A08G046_ADC1_ADRST_N 100
|
||||
#define R9A08G046_TSU_PRESETN 101
|
||||
#define R9A08G046_PDM_PRESETN 102
|
||||
#define R9A08G046_PCI_ARESETN 103
|
||||
#define R9A08G046_SPDIF_RST 104
|
||||
#define R9A08G046_I3C_TRESETN 105
|
||||
#define R9A08G046_I3C_PRESETN 106
|
||||
#define R9A08G046_VBAT_BRESETN 107
|
||||
#define R9A08G046_RSCI0_PRESETN 108
|
||||
#define R9A08G046_RSCI1_PRESETN 109
|
||||
#define R9A08G046_RSCI2_PRESETN 110
|
||||
#define R9A08G046_RSCI3_PRESETN 111
|
||||
#define R9A08G046_RSCI0_TRESETN 112
|
||||
#define R9A08G046_RSCI1_TRESETN 113
|
||||
#define R9A08G046_RSCI2_TRESETN 114
|
||||
#define R9A08G046_RSCI3_TRESETN 115
|
||||
#define R9A08G046_LVDS_RESET_N 116
|
||||
#define R9A08G046_BSC_X_PRESET_BSC 117
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */
|
||||
49
include/dt-bindings/reset/econet,en751221-scu.h
Normal file
49
include/dt-bindings/reset/econet,en751221-scu.h
Normal file
@@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
|
||||
#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
|
||||
#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
|
||||
|
||||
#define EN751221_XPON_PHY_RST 0
|
||||
#define EN751221_PCM1_ZSI_ISI_RST 1
|
||||
#define EN751221_FE_QDMA1_RST 2
|
||||
#define EN751221_FE_QDMA2_RST 3
|
||||
#define EN751221_FE_UNZIP_RST 4
|
||||
#define EN751221_PCM2_RST 5
|
||||
#define EN751221_PTM_MAC_RST 6
|
||||
#define EN751221_CRYPTO_RST 7
|
||||
#define EN751221_SAR_RST 8
|
||||
#define EN751221_TIMER_RST 9
|
||||
#define EN751221_INTC_RST 10
|
||||
#define EN751221_BONDING_RST 11
|
||||
#define EN751221_PCM1_RST 12
|
||||
#define EN751221_UART_RST 13
|
||||
#define EN751221_GPIO_RST 14
|
||||
#define EN751221_GDMA_RST 15
|
||||
#define EN751221_I2C_MASTER_RST 16
|
||||
#define EN751221_PCM2_ZSI_ISI_RST 17
|
||||
#define EN751221_SFC_RST 18
|
||||
#define EN751221_UART2_RST 19
|
||||
#define EN751221_GDMP_RST 20
|
||||
#define EN751221_FE_RST 21
|
||||
#define EN751221_USB_HOST_P0_RST 22
|
||||
#define EN751221_GSW_RST 23
|
||||
#define EN751221_SFC2_PCM_RST 24
|
||||
#define EN751221_PCIE0_RST 25
|
||||
#define EN751221_PCIE1_RST 26
|
||||
#define EN751221_CPU_TIMER_RST 27
|
||||
#define EN751221_PCIE_HB_RST 28
|
||||
#define EN751221_SIMIF_RST 29
|
||||
#define EN751221_XPON_MAC_RST 30
|
||||
#define EN751221_GFAST_RST 31
|
||||
#define EN751221_CPU_TIMER2_RST 32
|
||||
#define EN751221_UART3_RST 33
|
||||
#define EN751221_UART4_RST 34
|
||||
#define EN751221_UART5_RST 35
|
||||
#define EN751221_I2C2_RST 36
|
||||
#define EN751221_XSI_MAC_RST 37
|
||||
#define EN751221_XSI_PHY_RST 38
|
||||
#define EN751221_DMT_RST 39
|
||||
#define EN751221_USB_PHY_P0_RST 40
|
||||
#define EN751221_USB_PHY_P1_RST 41
|
||||
|
||||
#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */
|
||||
@@ -947,6 +947,26 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
|
||||
(parent_hw), NULL, (flags), (reg), \
|
||||
(shift), (width), (clk_divider_flags), \
|
||||
NULL, (lock))
|
||||
/**
|
||||
* devm_clk_hw_register_divider_parent_data - register a divider clock with the
|
||||
* clock framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_data: parent clk data
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define devm_clk_hw_register_divider_parent_data(dev, name, parent_data, \
|
||||
flags, reg, shift, width, \
|
||||
clk_divider_flags, lock) \
|
||||
__devm_clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
|
||||
(parent_data), (flags), (reg), (shift), \
|
||||
(width), (clk_divider_flags), NULL, \
|
||||
(lock))
|
||||
/**
|
||||
* devm_clk_hw_register_divider_table - register a table based divider clock
|
||||
* with the clock framework (devres variant)
|
||||
|
||||
Reference in New Issue
Block a user