mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-10 10:20:17 -04:00
arm64: dts: exynos: Add Exynos9810 SoC support
Exynos 9810 is an ARMv8 mobile SoC found in various Samsung devices, such as Samsung Galaxy S9 (starlte), S9 Plus (star2lte), Note 9 (crownlte) and perhaps others. Add minimal support for this SoC, including basic stuff like: - PSCI for bringing up secondary cores - ARMv8 generic timer - GPIO and pinctrl. The firmware coming with the devices based on this SoC is buggy and doesn't configure CNTFRQ_EL0, as required by spec, so it's needed to hardcode the frequency in the timer node. Co-developed-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Maksym Holovach <nergzd@nergzd723.xyz> Signed-off-by: Markuss Broks <markuss.broks@gmail.com> Link: https://lore.kernel.org/r/20241214-exynos9810-v4-1-4e91fbbc2133@gmail.com [krzysztof: Rename and move PMU nodes to proper sorting position] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Markuss Broks
committed by
Krzysztof Kozlowski
Krzysztof Kozlowski
parent
11fd6c9b04
commit
698be6fe8f
503
arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi
Normal file
503
arch/arm64/boot/dts/exynos/exynos9810-pinctrl.dtsi
Normal file
@@ -0,0 +1,503 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Samsung's Exynos 9810 SoC pin-mux and pin-config device tree source
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*
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* Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
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* Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
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*/
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#include "exynos-pinctrl.h"
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&pinctrl_alive {
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etc1: etc1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpa0: gpa0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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};
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gpa1: gpa1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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};
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gpa2: gpa2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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};
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gpa3: gpa3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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};
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gpa4: gpa4-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpq0: gpq0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_aud {
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gpb0: gpb0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpb1: gpb1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpb2: gpb2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_chub {
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gph0: gph0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gph1: gph1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_cmgp {
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gpm0: gpm0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm1: gpm1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm2: gpm2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm3: gpm3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm4: gpm4-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm5: gpm5-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm6: gpm6-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm7: gpm7-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm10: gpm10-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm11: gpm11-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm12: gpm12-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm13: gpm13-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm14: gpm14-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm15: gpm15-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm16: gpm16-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm17: gpm17-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm40: gpm40-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm41: gpm41-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm42: gpm42-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpm43: gpm43-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&pinctrl_fsys0 {
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gpf0: gpf0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_fsys1 {
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gpf1: gpf1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf2: gpf2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_peric0 {
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gpg0: gpg0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpg1: gpg1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpg2: gpg2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpp0: gpp0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpp1: gpp1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpp2: gpp2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpp3: gpp3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_peric1 {
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gpc0: gpc0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpc1: gpc1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
|
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};
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gpd0: gpd0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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|
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interrupt-controller;
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#interrupt-cells = <2>;
|
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};
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|
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gpg3: gpg3-gpio-bank {
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
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|
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interrupt-controller;
|
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#interrupt-cells = <2>;
|
||||
};
|
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|
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gpp4: gpp4-gpio-bank {
|
||||
gpio-controller;
|
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#gpio-cells = <2>;
|
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|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
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|
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gpp5: gpp5-gpio-bank {
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
||||
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
|
||||
};
|
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|
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gpp6: gpp6-gpio-bank {
|
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gpio-controller;
|
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#gpio-cells = <2>;
|
||||
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
|
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};
|
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};
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|
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&pinctrl_vts {
|
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gpt0: gpt0-gpio-bank {
|
||||
gpio-controller;
|
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#gpio-cells = <2>;
|
||||
|
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
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};
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273
arch/arm64/boot/dts/exynos/exynos9810.dtsi
Normal file
273
arch/arm64/boot/dts/exynos/exynos9810.dtsi
Normal file
@@ -0,0 +1,273 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
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/*
|
||||
* Samsung Exynos 9810 SoC device tree source
|
||||
*
|
||||
* Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
|
||||
* Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
|
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*/
|
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|
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#include <dt-bindings/interrupt-controller/arm-gic.h>
|
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|
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/ {
|
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compatible = "samsung,exynos9810";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
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|
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aliases {
|
||||
pinctrl0 = &pinctrl_alive;
|
||||
pinctrl1 = &pinctrl_aud;
|
||||
pinctrl2 = &pinctrl_chub;
|
||||
pinctrl3 = &pinctrl_cmgp;
|
||||
pinctrl4 = &pinctrl_fsys0;
|
||||
pinctrl5 = &pinctrl_fsys1;
|
||||
pinctrl6 = &pinctrl_peric0;
|
||||
pinctrl7 = &pinctrl_peric1;
|
||||
pinctrl8 = &pinctrl_vts;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x2>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x3>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x102>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "samsung,mongoose-m3";
|
||||
reg = <0x103>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
oscclk: osc-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "oscclk";
|
||||
};
|
||||
|
||||
pmu-a55 {
|
||||
compatible = "arm,cortex-a55-pmu";
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
pmu-mongoose-m3 {
|
||||
compatible = "samsung,mongoose-pmu";
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu4>,
|
||||
<&cpu5>,
|
||||
<&cpu6>,
|
||||
<&cpu7>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
cpu_off = <0x84000002>;
|
||||
cpu_on = <0xc4000003>;
|
||||
cpu_suspend = <0xc4000001>;
|
||||
};
|
||||
|
||||
soc: soc@0 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0x0 0x0 0x20000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chipid@10000000 {
|
||||
compatible = "samsung,exynos9810-chipid",
|
||||
"samsung,exynos850-chipid";
|
||||
reg = <0x10000000 0x100>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10101000 {
|
||||
compatible = "arm,gic-400";
|
||||
reg = <0x10101000 0x1000>,
|
||||
<0x10102000 0x1000>,
|
||||
<0x10104000 0x2000>,
|
||||
<0x10106000 0x2000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_peric0: pinctrl@10430000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x10430000 0x1000>;
|
||||
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_peric1: pinctrl@10830000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x10830000 0x1000>;
|
||||
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_fsys0: pinctrl@11050000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x11050000 0x1000>;
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_fsys1: pinctrl@11430000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x11430000 0x1000>;
|
||||
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_vts: pinctrl@13880000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x13880000 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl_chub: pinctrl@13a80000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x13a80000 0x1000>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pinctrl_alive: pinctrl@14050000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x14050000 0x1000>;
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos9810-wakeup-eint",
|
||||
"samsung,exynos850-wakeup-eint",
|
||||
"samsung,exynos7-wakeup-eint";
|
||||
};
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@14060000 {
|
||||
compatible = "samsung,exynos9810-pmu",
|
||||
"samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x14060000 0x10000>;
|
||||
};
|
||||
|
||||
pinctrl_cmgp: pinctrl@14220000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x14220000 0x1000>;
|
||||
|
||||
wakeup-interrupt-controller {
|
||||
compatible = "samsung,exynos9810-wakeup-eint",
|
||||
"samsung,exynos850-wakeup-eint",
|
||||
"samsung,exynos7-wakeup-eint";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_aud: pinctrl@17c60000 {
|
||||
compatible = "samsung,exynos9810-pinctrl";
|
||||
reg = <0x17c60000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
/* Hypervisor Virtual Timer interrupt is not wired to GIC */
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
/*
|
||||
* Non-updatable, broken stock Samsung bootloader does not
|
||||
* configure CNTFRQ_EL0
|
||||
*/
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "exynos9810-pinctrl.dtsi"
|
||||
#include "arm/samsung/exynos-syscon-restart.dtsi"
|
||||
Reference in New Issue
Block a user