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drm/mediatek: gamma: Program gamma LUT type for descending or rising
All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Reviewed-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20231012095736.100784-14-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
This commit is contained in:
committed by
Chun-Kuang Hu
parent
921e902b2c
commit
692e1a08ae
@@ -22,6 +22,7 @@
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#define GAMMA_RELAY_MODE BIT(0)
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#define GAMMA_LUT_EN BIT(1)
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#define GAMMA_DITHERING BIT(2)
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#define GAMMA_LUT_TYPE BIT(2)
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#define DISP_GAMMA_SIZE 0x0030
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#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16)
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#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0)
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@@ -82,6 +83,17 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev)
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return 0;
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}
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static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size)
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{
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u64 first, last;
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int last_entry = lut_size - 1;
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first = lut[0].red + lut[0].green + lut[0].blue;
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last = lut[last_entry].red + lut[last_entry].green + lut[last_entry].blue;
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return !!(first > last);
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}
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/*
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* SoCs supporting 12-bits LUTs are using a new register layout that does
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* always support (by HW) both 12-bits and 10-bits LUT but, on those, we
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@@ -173,6 +185,14 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)
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cfg_val = readl(gamma->regs + DISP_GAMMA_CFG);
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if (!gamma->data->has_dither) {
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/* Descending or Rising LUT */
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if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1))
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cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1);
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else
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cfg_val &= ~GAMMA_LUT_TYPE;
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}
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/* Enable the gamma table */
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cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1);
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