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drm/xe: Fix whitespace in register definitions

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Our register headers use tabs to align the definition values.  Convert a
few definitions that were using spaces instead.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-13-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper
2023-12-14 10:47:03 -08:00
committed by Rodrigo Vivi
parent 5ea7fe65fb
commit 68df8642ea
2 changed files with 5 additions and 5 deletions
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4
drivers/gpu/drm/xe/regs/xe_engine_regs.h
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@@ -136,8 +136,8 @@
#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
#define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10)
#define IECPUNIT_CLKGATE_DIS REG_BIT(22)

6
drivers/gpu/drm/xe/regs/xe_regs.h
View File

@@ -34,9 +34,9 @@
#define XEHPC_BCS7_RING_BASE 0x3ec000
#define XEHPC_BCS8_RING_BASE 0x3ee000
#define DG1_GSC_HECI2_BASE 0x00259000
#define PVC_GSC_HECI2_BASE 0x00285000
#define DG2_GSC_HECI2_BASE 0x00374000
#define DG1_GSC_HECI2_BASE 0x00259000
#define PVC_GSC_HECI2_BASE 0x00285000
#define DG2_GSC_HECI2_BASE 0x00374000
#define GSCCS_RING_BASE 0x11a000
#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)