drm/amd/display: Ensure array index tg_inst won't be -1

[WHY & HOW]
tg_inst will be a negative if timing_generator_count equals 0, which
should be checked before used.

This fixes 2 OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Hung
2024-04-16 16:44:17 -06:00
committed by Alex Deucher
parent 9419da1722
commit 687fe329f1

View File

@@ -3542,7 +3542,7 @@ static bool acquire_otg_master_pipe_for_stream(
if (pool->dpps[pipe_idx])
pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
if (pipe_idx >= pool->timing_generator_count) {
if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) {
int tg_inst = pool->timing_generator_count - 1;
pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];