mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-12 18:35:35 -04:00
PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
Add support for the i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe Endpoint (EP). On the i.MX8Q platforms, the PCI bus addresses differ from the CPU addresses. However, the DesignWare (DWC) driver already handles this in the common code. Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-7-c4bfa5193288@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
@@ -70,6 +70,7 @@ enum imx_pcie_variants {
|
||||
IMX8MQ_EP,
|
||||
IMX8MM_EP,
|
||||
IMX8MP_EP,
|
||||
IMX8Q_EP,
|
||||
IMX95_EP,
|
||||
};
|
||||
|
||||
@@ -1082,6 +1083,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
|
||||
.align = SZ_64K,
|
||||
};
|
||||
|
||||
static const struct pci_epc_features imx8q_pcie_epc_features = {
|
||||
.linkup_notifier = false,
|
||||
.msi_capable = true,
|
||||
.msix_capable = false,
|
||||
.bar[BAR_1] = { .type = BAR_RESERVED, },
|
||||
.bar[BAR_3] = { .type = BAR_RESERVED, },
|
||||
.bar[BAR_5] = { .type = BAR_RESERVED, },
|
||||
.align = SZ_64K,
|
||||
};
|
||||
|
||||
/*
|
||||
* BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme
|
||||
* ================================================================================================
|
||||
@@ -1678,6 +1689,14 @@ static const struct imx_pcie_drvdata drvdata[] = {
|
||||
.epc_features = &imx8m_pcie_epc_features,
|
||||
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
|
||||
},
|
||||
[IMX8Q_EP] = {
|
||||
.variant = IMX8Q_EP,
|
||||
.flags = IMX_PCIE_FLAG_HAS_PHYDRV,
|
||||
.mode = DW_PCIE_EP_TYPE,
|
||||
.epc_features = &imx8q_pcie_epc_features,
|
||||
.clk_names = imx8q_clks,
|
||||
.clks_cnt = ARRAY_SIZE(imx8q_clks),
|
||||
},
|
||||
[IMX95_EP] = {
|
||||
.variant = IMX95_EP,
|
||||
.flags = IMX_PCIE_FLAG_HAS_SERDES |
|
||||
@@ -1707,6 +1726,7 @@ static const struct of_device_id imx_pcie_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
|
||||
{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
|
||||
{ .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
|
||||
{ .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
|
||||
{ .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
|
||||
{},
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user