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drm/amd/display: Force prefetch mode to 0

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[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.

[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max prefetch mode to 0 by default.

Signed-off-by: Isabel Zhang <isabel.zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Isabel Zhang
2020-10-16 10:55:54 -04:00
committed by Alex Deucher
parent 850d2fcf3e
commit 685b4d8142
1 changed files with 3 additions and 1 deletions
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4
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
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@@ -301,7 +301,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.xfc_bus_transport_time_us = 4,
.xfc_xbuf_latency_tolerance_us = 4,
.use_urgent_burst_bw = 1,
.num_states = 8
.num_states = 8,
.allow_dram_self_refresh_or_dram_clock_change_in_vblank
= dm_allow_self_refresh_and_mclk_switch
};
#ifndef MAX