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Merge tag 'imx-soc-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

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The i.MX SoC updates for 4.13:
 - Select GPCv2 for i.MX7 SoCs to get imx-gpcv2 irqchip driver built
   for i.MX7 platforms by default.
 - A couple of patches from Leonard to add IMX6ULL cpu check and get
   suspend/resume work on IMX6ULL.

* tag 'imx-soc-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx6ull: Make suspend/resume work like on 6ul
  ARM: imx: Add MXC_CPU_IMX6ULL and cpu_is_imx6ull
  ARM: imx: Select GPCv2 for i.MX7

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2017-06-18 23:06:06 -07:00
parent 5a55029f46 bf5a01d7c5
commit 67a87a94f9
4 changed files with 14 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-imx/Kconfig
View File

@@ -536,6 +536,7 @@ config SOC_IMX7D
select HAVE_IMX_ANATOP
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select IMX_GPCV2
help
This enables support for Freescale i.MX7 Dual processor.

3
arch/arm/mach-imx/cpu.c
View File

@@ -131,6 +131,9 @@ struct device * __init imx_soc_device_init(void)
case MXC_CPU_IMX6UL:
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX7D:
soc_id = "i.MX7D";
break;

6
arch/arm/mach-imx/mxc.h
View File

@@ -39,6 +39,7 @@
#define MXC_CPU_IMX6SX 0x62
#define MXC_CPU_IMX6Q 0x63
#define MXC_CPU_IMX6UL 0x64
#define MXC_CPU_IMX6ULL 0x65
#define MXC_CPU_IMX7D 0x72
#define IMX_DDR_TYPE_LPDDR2 1
@@ -73,6 +74,11 @@ static inline bool cpu_is_imx6ul(void)
return __mxc_cpu_type == MXC_CPU_IMX6UL;
}
static inline bool cpu_is_imx6ull(void)
{
return __mxc_cpu_type == MXC_CPU_IMX6ULL;
}
static inline bool cpu_is_imx6q(void)
{
return __mxc_cpu_type == MXC_CPU_IMX6Q;

6
arch/arm/mach-imx/pm-imx6.c
View File

@@ -295,7 +295,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
val &= ~BM_CLPCR_SBYOS;
if (cpu_is_imx6sl())
val |= BM_CLPCR_BYPASS_PMIC_READY;
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
cpu_is_imx6ull())
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
else
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
@@ -312,7 +313,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
val |= BM_CLPCR_SBYOS;
if (cpu_is_imx6sl() || cpu_is_imx6sx())
val |= BM_CLPCR_BYPASS_PMIC_READY;
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
cpu_is_imx6ull())
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
else
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;