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drm/i915/cdclk: Rename intel_cdclk_needs_modeset to intel_cdclk_clock_changed
Looks like the name and description of intel_cdclk_needs_modeset() became inaccurate as of commit59f9e9cab3("drm/i915: Skip modeset for cdclk changes if possible"), when it became possible to update the cdclk without requiring disabling the pipes when only changing the cd2x divider was enough. Later on we also added the same type of support with squash and crawling with commit25e0e5ae56("drm/i915/display: Do both crawl and squash when changing cdclk"), commitd4a2393049("drm/i915: Allow cdclk squasher to be reconfigured live") and commitd62686ba3b("drm/i915/adl_p: CDCLK crawl support for ADL"). As such, update that function's name and documentation to something more appropriate, since the real checks for requiring modeset are done elsewhere. v2: - Rename to intel_cdclk_clock_changed instead of intel_cdclk_params_changed. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240214202719.298407-2-gustavo.sousa@intel.com
This commit is contained in:
committed by
Matt Roper
parent
2e56e34d0d
commit
669cf07d83
@@ -2260,16 +2260,15 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
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}
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/**
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* intel_cdclk_needs_modeset - Determine if changong between the CDCLK
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* configurations requires a modeset on all pipes
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* intel_cdclk_clock_changed - Check whether the clock changed
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* @a: first CDCLK configuration
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* @b: second CDCLK configuration
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*
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* Returns:
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* True if changing between the two CDCLK configurations
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* requires all pipes to be off, false if not.
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* True if CDCLK changed in a way that requires re-programming and
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* False otherwise.
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*/
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bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
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bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
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const struct intel_cdclk_config *b)
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{
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return a->cdclk != b->cdclk ||
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@@ -2322,7 +2321,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
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static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
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const struct intel_cdclk_config *b)
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{
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return intel_cdclk_needs_modeset(a, b) ||
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return intel_cdclk_clock_changed(a, b) ||
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a->voltage_level != b->voltage_level;
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}
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@@ -3229,7 +3228,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
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drm_dbg_kms(&dev_priv->drm,
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"Can change cdclk cd2x divider with pipe %c active\n",
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pipe_name(pipe));
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} else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
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} else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
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&new_cdclk_state->actual)) {
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/* All pipes must be switched off while we change the cdclk. */
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ret = intel_modeset_all_pipes_late(state, "CDCLK change");
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@@ -60,7 +60,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
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void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
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void intel_update_cdclk(struct drm_i915_private *dev_priv);
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u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
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bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
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bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
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const struct intel_cdclk_config *b);
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void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
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void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
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@@ -968,7 +968,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
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intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
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/* Can't read out voltage_level so can't use intel_cdclk_changed() */
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drm_WARN_ON(&dev_priv->drm,
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intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw,
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intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw,
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&cdclk_config));
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gen9_assert_dbuf_enabled(dev_priv);
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