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staging: brcm80211: make use of linux error codes in srom.c
The source file srom.c used meaningless non-zero numbers to return upon error conditions. These have been replaced by linux error codes. Signed-off-by: Arend van Spriel <arend@broadcom.com> Reviewed-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
fa0ace7fd3
commit
66671fc120
@@ -870,7 +870,7 @@ int srom_var_init(struct si_pub *sih, uint bustype, void *curmap,
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if (curmap != NULL && bustype == PCI_BUS)
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return initvars_srom_pci(sih, curmap, vars, count);
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return -1;
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return -EINVAL;
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}
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/* In chips with chipcommon rev 32 and later, the srom is in chipcommon,
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@@ -935,7 +935,7 @@ sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
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if (sih->ccrev > 31 && ISSIM_ENAB(sih)) {
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/* use indirect since direct is too slow on QT */
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if ((sih->cccaps & CC_CAP_SROM) == 0)
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return 1;
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return -ENODEV;
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ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
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buf[i] =
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@@ -953,7 +953,7 @@ sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
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/* bypass crc checking for simulation to allow srom hack */
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if (ISSIM_ENAB(sih))
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return err;
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return 0;
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if (check_crc) {
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@@ -962,7 +962,7 @@ sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
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* is blank, regardless of the rest of the content, so declare
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* it bad.
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*/
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return 1;
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return -ENODATA;
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}
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/* fixup the endianness so crc8 will pass */
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@@ -970,7 +970,7 @@ sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
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if (brcmu_crc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) !=
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CRC8_GOOD_VALUE) {
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/* DBG only pci always read srom4 first, then srom8/9 */
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err = 1;
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err = -EIO;
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}
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/* now correct the endianness of the byte array */
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ltoh16_buf(buf, nwords * 2);
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@@ -987,7 +987,7 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
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otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
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if (otp == NULL) {
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return -EBADE;
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return -ENOMEM;
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}
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err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
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@@ -1002,14 +1002,14 @@ static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
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* is blank, regardless of the rest of the content, so declare
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* it bad.
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*/
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return 1;
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return -ENODATA;
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}
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/* fixup the endianness so crc8 will pass */
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htol16_buf(buf, bufsz);
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if (brcmu_crc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) !=
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CRC8_GOOD_VALUE) {
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err = 1;
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err = -EIO;
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}
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/* now correct the endianness of the byte array */
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ltoh16_buf(buf, bufsz);
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@@ -1219,13 +1219,12 @@ static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
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*/
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srom = kmalloc(SROM_MAX, GFP_ATOMIC);
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if (!srom)
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return -2;
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return -ENOMEM;
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sromwindow = (u16 *) SROM_OFFSET(sih);
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if (ai_is_sprom_available(sih)) {
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err =
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sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
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true);
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err = sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
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true);
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if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
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(((sih->buscoretype == PCIE_CORE_ID)
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@@ -1233,9 +1232,8 @@ static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
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|| ((sih->buscoretype == PCI_CORE_ID)
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&& (sih->buscorerev >= 0xe)))) {
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/* sromrev >= 4, read more */
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err =
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sprom_read_pci(sih, sromwindow, 0, srom,
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SROM4_WORDS, true);
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err = sprom_read_pci(sih, sromwindow, 0, srom,
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SROM4_WORDS, true);
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sromrev = srom[SROM4_CRCREV] & 0xff;
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} else if (err == 0) {
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/* srom is good and is rev < 4 */
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@@ -1253,12 +1251,10 @@ static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
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if (err == 0)
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/* OTP only contain SROM rev8/rev9 for now */
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sromrev = srom[SROM4_CRCREV] & 0xff;
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else
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err = 1;
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}
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#else
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else
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err = 1;
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err = -ENODEV;
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#endif
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if (!err) {
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@@ -1267,13 +1263,13 @@ static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
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/* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */
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if ((sr & 0x33e) == 0) {
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err = -2;
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err = -EINVAL;
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goto errout;
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}
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base = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
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if (!base) {
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err = -2;
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err = -ENOMEM;
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goto errout;
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}
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