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drm/i915/scaler: Limit pipe scaler downscaling factors for YUV420

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Limit downscaling to less than 1.5 (source/destination) in
the horizontal direction and 1.0 in the vertical direction,
When configured for Pipe YUV 420 encoding for port output.

Bspec: 50441, 7490, 69901
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120172209.188488-6-mitulkumar.ajitkumar.golani@intel.com
This commit is contained in:
Mitul Golani
2025-01-20 22:52:06 +05:30
committed by Ankit Nautiyal
parent 9217f9aaef
commit 65599f65b4
1 changed files with 10 additions and 0 deletions
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10
drivers/gpu/drm/i915/display/skl_scaler.c
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@@ -459,6 +459,16 @@ static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state,
calculate_max_scale(crtc, 0, *scaler_id,
&max_hscale, &max_vscale);
/*
* When configured for Pipe YUV 420 encoding for port output,
* limit downscaling to less than 1.5 (source/destination) in
* the horizontal direction and 1.0 in the vertical direction.
*/
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
max_hscale = 0x18000 - 1;
max_vscale = 0x10000;
}
hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst,
0, max_hscale);
vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst,