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arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets

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Asserting the NOCSR reset line keeps the PHY registers in tact.
This allows us to avoid programming long tables of magic values in the
operating system.

Wire up these resets to PCIe PHY4 and 5 (it's there on the others).

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-4-72cd4cdc767b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio
2025-02-03 15:43:23 +01:00
committed by Bjorn Andersson
parent 467284a309
commit 62ca6669d6
1 changed files with 8 additions and 4 deletions
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12
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@@ -3558,8 +3558,10 @@ pcie5_phy: phy@1c06000 {
"pipe",
"pipediv2";
resets = <&gcc GCC_PCIE_5_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_5_PHY_BCR>,
<&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
reset-names = "phy",
"phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
@@ -3692,8 +3694,10 @@ pcie4_phy: phy@1c0e000 {
"pipe",
"pipediv2";
resets = <&gcc GCC_PCIE_4_PHY_BCR>;
reset-names = "phy";
resets = <&gcc GCC_PCIE_4_PHY_BCR>,
<&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
reset-names = "phy",
"phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;