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net: dsa: microchip: Use regs[] to access REG_PTP_CLK_CTRL
Accesses to the PTP_CLK_CTRL register are done through a hardcoded address which doesn't match with the KSZ8463's register layout. Add a new entry for the PTP_CLK_CTRL register in the regs[] tables. Use the regs[] table to retrieve the PTP_CLK_CTRL register address when accessing it. Remove the macro defining the address to prevent further use. Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com> Link: https://patch.msgid.link/20260105-ksz-rework-v1-3-a68df7f57375@bootlin.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
committed by
Paolo Abeni
parent
22bde912e8
commit
62382d6ffe
@@ -569,6 +569,7 @@ static const u16 ksz8463_regs[] = {
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[S_START_CTRL] = 0x01,
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[S_BROADCAST_CTRL] = 0x06,
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[S_MULTICAST_CTRL] = 0x04,
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[PTP_CLK_CTRL] = 0x0600,
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};
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static const u32 ksz8463_masks[] = {
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@@ -803,6 +804,7 @@ static const u16 ksz9477_regs[] = {
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[REG_SW_PME_CTRL] = 0x0006,
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[REG_PORT_PME_STATUS] = 0x0013,
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[REG_PORT_PME_CTRL] = 0x0017,
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[PTP_CLK_CTRL] = 0x0500,
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};
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static const u32 ksz9477_masks[] = {
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@@ -271,6 +271,7 @@ enum ksz_regs {
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REG_SW_PME_CTRL,
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REG_PORT_PME_STATUS,
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REG_PORT_PME_CTRL,
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PTP_CLK_CTRL,
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};
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enum ksz_masks {
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@@ -585,13 +585,14 @@ void ksz_port_deferred_xmit(struct kthread_work *work)
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static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts)
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{
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const u16 *regs = dev->info->regs;
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u32 nanoseconds;
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u32 seconds;
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u8 phase;
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int ret;
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/* Copy current PTP clock into shadow registers and read */
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ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_READ_TIME, PTP_READ_TIME);
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ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_READ_TIME, PTP_READ_TIME);
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if (ret)
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return ret;
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@@ -676,6 +677,7 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp,
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{
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struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data);
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const u16 *regs = dev->info->regs;
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int ret;
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mutex_lock(&ptp_data->lock);
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@@ -693,7 +695,7 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp,
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if (ret)
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goto unlock;
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ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_LOAD_TIME, PTP_LOAD_TIME);
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ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_LOAD_TIME, PTP_LOAD_TIME);
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if (ret)
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goto unlock;
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@@ -723,6 +725,7 @@ static int ksz_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data);
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const u16 *regs = dev->info->regs;
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u64 base, adj;
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bool negative;
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u32 data32;
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@@ -743,12 +746,12 @@ static int ksz_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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if (ret)
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goto unlock;
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ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE,
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ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ADJ_ENABLE,
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PTP_CLK_ADJ_ENABLE);
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if (ret)
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goto unlock;
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} else {
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ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE, 0);
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ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ADJ_ENABLE, 0);
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if (ret)
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goto unlock;
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}
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@@ -763,6 +766,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp);
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struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data);
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struct timespec64 delta64 = ns_to_timespec64(delta);
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const u16 *regs = dev->info->regs;
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s32 sec, nsec;
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u16 data16;
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int ret;
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@@ -782,7 +786,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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if (ret)
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goto unlock;
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ret = ksz_read16(dev, REG_PTP_CLK_CTRL, &data16);
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ret = ksz_read16(dev, regs[PTP_CLK_CTRL], &data16);
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if (ret)
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goto unlock;
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@@ -794,7 +798,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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else
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data16 |= PTP_STEP_DIR;
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ret = ksz_write16(dev, REG_PTP_CLK_CTRL, data16);
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ret = ksz_write16(dev, regs[PTP_CLK_CTRL], data16);
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if (ret)
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goto unlock;
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@@ -882,9 +886,10 @@ static long ksz_ptp_do_aux_work(struct ptp_clock_info *ptp)
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static int ksz_ptp_start_clock(struct ksz_device *dev)
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{
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struct ksz_ptp_data *ptp_data = &dev->ptp_data;
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const u16 *regs = dev->info->regs;
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int ret;
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ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ENABLE, PTP_CLK_ENABLE);
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ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ENABLE, PTP_CLK_ENABLE);
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if (ret)
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return ret;
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@@ -15,8 +15,7 @@
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#define LED_SRC_PTP_GPIO_2 BIT(2)
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/* 5 - PTP Clock */
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#define REG_PTP_CLK_CTRL 0x0500
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/* REG_PTP_CLK_CTRL */
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#define PTP_STEP_ADJ BIT(6)
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#define PTP_STEP_DIR BIT(5)
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#define PTP_READ_TIME BIT(4)
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