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staging: r8188eu: Add files for new driver - part 14
This commit adds files hal/rtl8188e_hal_init.c, hal/rtl8188e_mp.c, hal/rtl8188e_phycfg.c, and hal/rtl8188e_rf6052.c. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Larry Finger
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
7ef8ded0cf
commit
615a4d12e5
2378
drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c
Normal file
2378
drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c
Normal file
File diff suppressed because it is too large
Load Diff
860
drivers/staging/rtl8188eu/hal/rtl8188e_mp.c
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860
drivers/staging/rtl8188eu/hal/rtl8188e_mp.c
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@@ -0,0 +1,860 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#define _RTL8188E_MP_C_
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#include <drv_types.h>
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#include <rtw_mp.h>
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#include <rtl8188e_hal.h>
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#include <rtl8188e_dm.h>
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s32 Hal_SetPowerTracking(struct adapter *padapter, u8 enable)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
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struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
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if (!netif_running(padapter->pnetdev)) {
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RT_TRACE(_module_mp_, _drv_warning_,
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("SetPowerTracking! Fail: interface not opened!\n"));
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return _FAIL;
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}
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if (!check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE)) {
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RT_TRACE(_module_mp_, _drv_warning_,
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("SetPowerTracking! Fail: not in MP mode!\n"));
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return _FAIL;
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}
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if (enable)
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pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
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else
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pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
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return _SUCCESS;
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}
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void Hal_GetPowerTracking(struct adapter *padapter, u8 *enable)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
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struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
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*enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
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}
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/*-----------------------------------------------------------------------------
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* Function: mpt_SwitchRfSetting
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*
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* Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
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*
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* Input: struct adapter * pAdapter
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Revised History:
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* When Who Remark
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* 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
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* 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
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*
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*---------------------------------------------------------------------------*/
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void Hal_mpt_SwitchRfSetting(struct adapter *pAdapter)
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{
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struct mp_priv *pmp = &pAdapter->mppriv;
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/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. */
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pmp->MptCtx.backup0x52_RF_A = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
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pmp->MptCtx.backup0x52_RF_B = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
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PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
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PHY_SetRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
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return;
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}
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/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
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/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
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void Hal_MPT_CCKTxPowerAdjust(struct adapter *Adapter, bool bInCH14)
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{
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u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
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u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
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u8 i;
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/* get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
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CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
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if (!bInCH14) {
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/* Readback the current bb cck swing value and compare with the table to */
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/* get the current swing index */
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for (i = 0; i < CCK_TABLE_SIZE; i++) {
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if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
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(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
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CCKSwingIndex = i;
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break;
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}
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}
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/* Write 0xa22 0xa23 */
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TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8);
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/* Write 0xa24 ~ 0xa27 */
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TempVal2 = 0;
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TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16)+
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
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/* Write 0xa28 0xa29 */
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TempVal3 = 0;
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TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
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(CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8);
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} else {
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for (i = 0; i < CCK_TABLE_SIZE; i++) {
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if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
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(((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) {
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CCKSwingIndex = i;
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break;
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}
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}
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/* Write 0xa22 0xa23 */
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TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
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(CCKSwingTable_Ch14[CCKSwingIndex][1]<<8);
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/* Write 0xa24 ~ 0xa27 */
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TempVal2 = 0;
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TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
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(CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
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(CCKSwingTable_Ch14[CCKSwingIndex][4]<<16)+
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(CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
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/* Write 0xa28 0xa29 */
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TempVal3 = 0;
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TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
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(CCKSwingTable_Ch14[CCKSwingIndex][7]<<8);
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}
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write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
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write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
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write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
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}
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void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter *pAdapter, bool beven)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
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struct mpt_context *pMptCtx = &pAdapter->mppriv.MptCtx;
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struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
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s32 TempCCk;
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u8 CCK_index, CCK_index_old = 0;
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u8 Action = 0; /* 0: no action, 1: even->odd, 2:odd->even */
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s32 i = 0;
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if (!IS_92C_SERIAL(pHalData->VersionID))
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return;
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if (beven && !pMptCtx->bMptIndexEven) {
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/* odd->even */
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Action = 2;
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pMptCtx->bMptIndexEven = true;
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} else if (!beven && pMptCtx->bMptIndexEven) {
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/* even->odd */
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Action = 1;
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pMptCtx->bMptIndexEven = false;
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}
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if (Action != 0) {
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/* Query CCK default setting From 0xa24 */
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TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
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for (i = 0; i < CCK_TABLE_SIZE; i++) {
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if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
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if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch14[i][2], 4)) {
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CCK_index_old = (u8)i;
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break;
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}
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} else {
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if (_rtw_memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch1_Ch13[i][2], 4)) {
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CCK_index_old = (u8)i;
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break;
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}
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}
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}
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if (Action == 1)
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CCK_index = CCK_index_old - 1;
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else
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CCK_index = CCK_index_old + 1;
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/* Adjust CCK according to gain index */
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if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
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rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
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rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
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rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
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rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
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rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
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rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
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rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
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rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
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} else {
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rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
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rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
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rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
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rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
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rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
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rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
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rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
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rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
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}
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}
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}
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/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
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/*
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* SetChannel
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* Description
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* Use H2C command to change channel,
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* not only modify rf register, but also other setting need to be done.
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*/
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void Hal_SetChannel(struct adapter *pAdapter)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
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struct mp_priv *pmp = &pAdapter->mppriv;
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struct odm_dm_struct *pDM_Odm = &(pHalData->odmpriv);
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u8 eRFPath;
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u8 channel = pmp->channel;
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/* set RF channel register */
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for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
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_write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
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Hal_mpt_SwitchRfSetting(pAdapter);
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SelectChannel(pAdapter, channel);
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if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
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pDM_Odm->RFCalibrateInfo.bCCKinCH14 = true;
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Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
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} else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
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pDM_Odm->RFCalibrateInfo.bCCKinCH14 = false;
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Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
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}
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}
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/*
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* Notice
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* Switch bandwitdth may change center frequency(channel)
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*/
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void Hal_SetBandwidth(struct adapter *pAdapter)
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{
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struct mp_priv *pmp = &pAdapter->mppriv;
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SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
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Hal_mpt_SwitchRfSetting(pAdapter);
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}
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void Hal_SetCCKTxPower(struct adapter *pAdapter, u8 *TxPower)
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{
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u32 tmpval = 0;
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/* rf-A cck tx power */
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write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
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tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
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write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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/* rf-B cck tx power */
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write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
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tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
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write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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RT_TRACE(_module_mp_, _drv_notice_,
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("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
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TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
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}
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void Hal_SetOFDMTxPower(struct adapter *pAdapter, u8 *TxPower)
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{
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u32 TxAGC = 0;
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u8 tmpval = 0;
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/* HT Tx-rf(A) */
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tmpval = TxPower[RF_PATH_A];
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TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
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/* HT Tx-rf(B) */
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tmpval = TxPower[RF_PATH_B];
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TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
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write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
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write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
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}
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void Hal_SetAntennaPathPower(struct adapter *pAdapter)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
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u8 TxPowerLevel[MAX_RF_PATH_NUMS];
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u8 rfPath;
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TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
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TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
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switch (pAdapter->mppriv.antenna_tx) {
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case ANTENNA_A:
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default:
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rfPath = RF_PATH_A;
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break;
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case ANTENNA_B:
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rfPath = RF_PATH_B;
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break;
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case ANTENNA_C:
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rfPath = RF_PATH_C;
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break;
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}
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switch (pHalData->rf_chip) {
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case RF_8225:
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case RF_8256:
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case RF_6052:
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Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
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if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
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Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
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Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
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break;
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default:
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break;
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}
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}
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void Hal_SetTxPower(struct adapter *pAdapter)
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{
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struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
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u8 TxPower = pAdapter->mppriv.txpoweridx;
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u8 TxPowerLevel[MAX_RF_PATH_NUMS];
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u8 rf, rfPath;
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for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++)
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TxPowerLevel[rf] = TxPower;
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switch (pAdapter->mppriv.antenna_tx) {
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case ANTENNA_A:
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default:
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rfPath = RF_PATH_A;
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break;
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case ANTENNA_B:
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rfPath = RF_PATH_B;
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break;
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case ANTENNA_C:
|
||||
rfPath = RF_PATH_C;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (pHalData->rf_chip) {
|
||||
/* 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
|
||||
/* We should call normal driver API later!! */
|
||||
case RF_8225:
|
||||
case RF_8256:
|
||||
case RF_6052:
|
||||
Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
|
||||
if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
|
||||
Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
|
||||
Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void Hal_SetDataRate(struct adapter *pAdapter)
|
||||
{
|
||||
Hal_mpt_SwitchRfSetting(pAdapter);
|
||||
}
|
||||
|
||||
void Hal_SetAntenna(struct adapter *pAdapter)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
|
||||
|
||||
struct ant_sel_ofdm *p_ofdm_tx; /* OFDM Tx register */
|
||||
struct ant_sel_cck *p_cck_txrx;
|
||||
u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
|
||||
u8 chgTx = 0, chgRx = 0;
|
||||
u32 r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
|
||||
|
||||
|
||||
p_ofdm_tx = (struct ant_sel_ofdm *)&r_ant_select_ofdm_val;
|
||||
p_cck_txrx = (struct ant_sel_cck *)&r_ant_select_cck_val;
|
||||
|
||||
p_ofdm_tx->r_ant_ht1 = 0x1;
|
||||
p_ofdm_tx->r_ant_ht2 = 0x2; /* Second TX RF path is A */
|
||||
p_ofdm_tx->r_ant_non_ht = 0x3; /* 0x1+0x2=0x3 */
|
||||
|
||||
switch (pAdapter->mppriv.antenna_tx) {
|
||||
case ANTENNA_A:
|
||||
p_ofdm_tx->r_tx_antenna = 0x1;
|
||||
r_ofdm_tx_en_val = 0x1;
|
||||
p_ofdm_tx->r_ant_l = 0x1;
|
||||
p_ofdm_tx->r_ant_ht_s1 = 0x1;
|
||||
p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
|
||||
p_cck_txrx->r_ccktx_enable = 0x8;
|
||||
chgTx = 1;
|
||||
|
||||
/* From SD3 Willis suggestion !!! Set RF A=TX and B as standby */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
|
||||
r_ofdm_tx_en_val = 0x3;
|
||||
|
||||
/* Power save */
|
||||
|
||||
/* We need to close RFB by SW control */
|
||||
if (pHalData->rf_type == RF_2T2R) {
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
|
||||
}
|
||||
break;
|
||||
case ANTENNA_B:
|
||||
p_ofdm_tx->r_tx_antenna = 0x2;
|
||||
r_ofdm_tx_en_val = 0x2;
|
||||
p_ofdm_tx->r_ant_l = 0x2;
|
||||
p_ofdm_tx->r_ant_ht_s1 = 0x2;
|
||||
p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
|
||||
p_cck_txrx->r_ccktx_enable = 0x4;
|
||||
chgTx = 1;
|
||||
/* From SD3 Willis suggestion !!! Set RF A as standby */
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
|
||||
|
||||
/* Power save */
|
||||
/* cosa r_ant_select_ofdm_val = 0x22222222; */
|
||||
|
||||
/* 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
|
||||
/* 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
|
||||
if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
|
||||
}
|
||||
break;
|
||||
case ANTENNA_AB: /* For 8192S */
|
||||
p_ofdm_tx->r_tx_antenna = 0x3;
|
||||
r_ofdm_tx_en_val = 0x3;
|
||||
p_ofdm_tx->r_ant_l = 0x3;
|
||||
p_ofdm_tx->r_ant_ht_s1 = 0x3;
|
||||
p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
|
||||
p_cck_txrx->r_ccktx_enable = 0xC;
|
||||
chgTx = 1;
|
||||
|
||||
/* From SD3 Willis suggestion !!! Set RF B as standby */
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
|
||||
|
||||
/* Disable Power save */
|
||||
/* cosa r_ant_select_ofdm_val = 0x3321333; */
|
||||
/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
|
||||
if (pHalData->rf_type == RF_2T2R) {
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
|
||||
/* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
|
||||
/* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
|
||||
switch (pAdapter->mppriv.antenna_rx) {
|
||||
case ANTENNA_A:
|
||||
r_rx_antenna_ofdm = 0x1; /* A */
|
||||
p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
|
||||
chgRx = 1;
|
||||
break;
|
||||
case ANTENNA_B:
|
||||
r_rx_antenna_ofdm = 0x2; /* B */
|
||||
p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
|
||||
chgRx = 1;
|
||||
break;
|
||||
case ANTENNA_AB:
|
||||
r_rx_antenna_ofdm = 0x3; /* AB */
|
||||
p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
|
||||
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
|
||||
chgRx = 1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (chgTx && chgRx) {
|
||||
switch (pHalData->rf_chip) {
|
||||
case RF_8225:
|
||||
case RF_8256:
|
||||
case RF_6052:
|
||||
/* r_ant_sel_cck_val = r_ant_select_cck_val; */
|
||||
PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /* OFDM Tx */
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /* OFDM Tx */
|
||||
PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
|
||||
PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
|
||||
PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val); /* CCK TxRx */
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
|
||||
}
|
||||
|
||||
s32 Hal_SetThermalMeter(struct adapter *pAdapter, u8 target_ther)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
|
||||
|
||||
|
||||
if (!netif_running(pAdapter->pnetdev)) {
|
||||
RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == false) {
|
||||
RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
target_ther &= 0xff;
|
||||
if (target_ther < 0x07)
|
||||
target_ther = 0x07;
|
||||
else if (target_ther > 0x1d)
|
||||
target_ther = 0x1d;
|
||||
|
||||
pHalData->EEPROMThermalMeter = target_ther;
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
void Hal_TriggerRFThermalMeter(struct adapter *pAdapter)
|
||||
{
|
||||
_write_rfreg(pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 | BIT16 , 0x03);
|
||||
}
|
||||
|
||||
u8 Hal_ReadRFThermalMeter(struct adapter *pAdapter)
|
||||
{
|
||||
u32 ThermalValue = 0;
|
||||
|
||||
ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);
|
||||
return (u8)ThermalValue;
|
||||
}
|
||||
|
||||
void Hal_GetThermalMeter(struct adapter *pAdapter, u8 *value)
|
||||
{
|
||||
Hal_TriggerRFThermalMeter(pAdapter);
|
||||
rtw_msleep_os(1000);
|
||||
*value = Hal_ReadRFThermalMeter(pAdapter);
|
||||
}
|
||||
|
||||
void Hal_SetSingleCarrierTx(struct adapter *pAdapter, u8 bStart)
|
||||
{
|
||||
pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
|
||||
if (bStart) {
|
||||
/* Start Single Carrier. */
|
||||
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
|
||||
/* 1. if OFDM block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
|
||||
|
||||
/* 2. set CCK test mode off, set to CCK normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
|
||||
/* 3. turn on scramble setting */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
||||
/* 4. Turn On Single Carrier Tx and turn off the other test modes. */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
} else {
|
||||
/* Stop Single Carrier. */
|
||||
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test stop\n"));
|
||||
|
||||
/* Turn off all test modes. */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
rtw_msleep_os(10);
|
||||
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Hal_SetSingleToneTx(struct adapter *pAdapter, u8 bStart)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
|
||||
bool is92C = IS_92C_SERIAL(pHalData->VersionID);
|
||||
|
||||
u8 rfPath;
|
||||
u32 reg58 = 0x0;
|
||||
switch (pAdapter->mppriv.antenna_tx) {
|
||||
case ANTENNA_A:
|
||||
default:
|
||||
rfPath = RF_PATH_A;
|
||||
break;
|
||||
case ANTENNA_B:
|
||||
rfPath = RF_PATH_B;
|
||||
break;
|
||||
case ANTENNA_C:
|
||||
rfPath = RF_PATH_C;
|
||||
break;
|
||||
}
|
||||
|
||||
pAdapter->mppriv.MptCtx.bSingleTone = bStart;
|
||||
if (bStart) {
|
||||
/* Start Single Tone. */
|
||||
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test start\n"));
|
||||
/* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
|
||||
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
|
||||
reg58 &= 0xFFFFFFF0;
|
||||
reg58 += 2;
|
||||
PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
|
||||
}
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
|
||||
PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
|
||||
|
||||
if (is92C) {
|
||||
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
|
||||
rtw_usleep_os(100);
|
||||
if (rfPath == RF_PATH_A)
|
||||
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); /* PAD all on. */
|
||||
else if (rfPath == RF_PATH_B)
|
||||
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /* PAD all on. */
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
} else {
|
||||
write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
|
||||
rtw_usleep_os(100);
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
}
|
||||
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
} else {
|
||||
/* Stop Single Tone. */
|
||||
RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleToneTx: test stop\n"));
|
||||
|
||||
/* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
|
||||
/* <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
|
||||
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
|
||||
reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
|
||||
reg58 &= 0xFFFFFFF0;
|
||||
PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
|
||||
}
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
|
||||
if (is92C) {
|
||||
_write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
|
||||
rtw_usleep_os(100);
|
||||
write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); /* PAD all on. */
|
||||
write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
} else {
|
||||
write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
|
||||
rtw_usleep_os(100);
|
||||
write_rfreg(pAdapter, rfPath, 0x00, 0x30000); /* PAD all on. */
|
||||
rtw_usleep_os(100);
|
||||
}
|
||||
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
void Hal_SetCarrierSuppressionTx(struct adapter *pAdapter, u8 bStart)
|
||||
{
|
||||
pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
|
||||
if (bStart) {
|
||||
/* Start Carrier Suppression. */
|
||||
RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
|
||||
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
|
||||
/* 1. if CCK block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
|
||||
|
||||
/* Turn Off All Test Mode */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /* turn off scramble setting */
|
||||
|
||||
/* Set CCK Tx Test Rate */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /* Set FTxRate to 1Mbps */
|
||||
}
|
||||
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
} else {
|
||||
/* Stop Carrier Suppression. */
|
||||
RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
|
||||
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /* turn on scramble setting */
|
||||
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
}
|
||||
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
}
|
||||
}
|
||||
|
||||
void Hal_SetCCKContinuousTx(struct adapter *pAdapter, u8 bStart)
|
||||
{
|
||||
u32 cckrate;
|
||||
|
||||
if (bStart) {
|
||||
RT_TRACE(_module_mp_, _drv_alert_,
|
||||
("SetCCKContinuousTx: test start\n"));
|
||||
|
||||
/* 1. if CCK block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
|
||||
|
||||
/* Turn Off All Test Mode */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
/* Set CCK Tx Test Rate */
|
||||
cckrate = pAdapter->mppriv.rateidx;
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
|
||||
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
} else {
|
||||
RT_TRACE(_module_mp_, _drv_info_,
|
||||
("SetCCKContinuousTx: test stop\n"));
|
||||
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
|
||||
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
}
|
||||
|
||||
pAdapter->mppriv.MptCtx.bCckContTx = bStart;
|
||||
pAdapter->mppriv.MptCtx.bOfdmContTx = false;
|
||||
} /* mpt_StartCckContTx */
|
||||
|
||||
void Hal_SetOFDMContinuousTx(struct adapter *pAdapter, u8 bStart)
|
||||
{
|
||||
if (bStart) {
|
||||
RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
|
||||
/* 1. if OFDM block on? */
|
||||
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
|
||||
write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
|
||||
|
||||
/* 2. set CCK test mode off, set to CCK normal mode */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
|
||||
|
||||
/* 3. turn on scramble setting */
|
||||
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
||||
/* 4. Turn On Continue Tx and turn off the other test modes. */
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
|
||||
/* for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
|
||||
|
||||
} else {
|
||||
RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
||||
write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
||||
/* Delay 10 ms */
|
||||
rtw_msleep_os(10);
|
||||
/* BB Reset */
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
||||
write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
||||
|
||||
/* Stop for dynamic set Power index. */
|
||||
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
|
||||
}
|
||||
|
||||
pAdapter->mppriv.MptCtx.bCckContTx = false;
|
||||
pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
|
||||
} /* mpt_StartOfdmContTx */
|
||||
|
||||
void Hal_SetContinuousTx(struct adapter *pAdapter, u8 bStart)
|
||||
{
|
||||
RT_TRACE(_module_mp_, _drv_info_,
|
||||
("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
|
||||
|
||||
pAdapter->mppriv.MptCtx.bStartContTx = bStart;
|
||||
if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
|
||||
Hal_SetCCKContinuousTx(pAdapter, bStart);
|
||||
else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
|
||||
(pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
|
||||
Hal_SetOFDMContinuousTx(pAdapter, bStart);
|
||||
}
|
||||
1144
drivers/staging/rtl8188eu/hal/rtl8188e_phycfg.c
Normal file
1144
drivers/staging/rtl8188eu/hal/rtl8188e_phycfg.c
Normal file
File diff suppressed because it is too large
Load Diff
572
drivers/staging/rtl8188eu/hal/rtl8188e_rf6052.c
Normal file
572
drivers/staging/rtl8188eu/hal/rtl8188e_rf6052.c
Normal file
@@ -0,0 +1,572 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
*
|
||||
*
|
||||
* Module: rtl8192c_rf6052.c ( Source C File)
|
||||
*
|
||||
* Note: Provide RF 6052 series relative API.
|
||||
*
|
||||
* Function:
|
||||
*
|
||||
* Export:
|
||||
*
|
||||
* Abbrev:
|
||||
*
|
||||
* History:
|
||||
* Data Who Remark
|
||||
*
|
||||
* 09/25/2008 MHC Create initial version.
|
||||
* 11/05/2008 MHC Add API for tw power setting.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#define _RTL8188E_RF6052_C_
|
||||
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
#include <rtl8188e_hal.h>
|
||||
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
/* Define local structure for debug!!!!! */
|
||||
struct rf_shadow {
|
||||
/* Shadow register value */
|
||||
u32 Value;
|
||||
/* Compare or not flag */
|
||||
u8 Compare;
|
||||
/* Record If it had ever modified unpredicted */
|
||||
u8 ErrorOrNot;
|
||||
/* Recorver Flag */
|
||||
u8 Recorver;
|
||||
/* */
|
||||
u8 Driver_Write;
|
||||
};
|
||||
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
|
||||
|
||||
/*------------------------Define global variable-----------------------------*/
|
||||
|
||||
/*------------------------Define local variable------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: RF_ChangeTxPath
|
||||
*
|
||||
* Overview: For RL6052, we must change some RF settign for 1T or 2T.
|
||||
*
|
||||
* Input: u16 DataRate 0x80-8f, 0x90-9f
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 09/25/2008 MHC Create Version 0.
|
||||
* Firmwaer support the utility later.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
void rtl8188e_RF_ChangeTxPath(struct adapter *Adapter, u16 DataRate)
|
||||
{
|
||||
/* We do not support gain table change inACUT now !!!! Delete later !!! */
|
||||
} /* RF_ChangeTxPath */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: PHY_RF6052SetBandwidth()
|
||||
*
|
||||
* Overview: This function is called by SetBWModeCallback8190Pci() only
|
||||
*
|
||||
* Input: struct adapter *Adapter
|
||||
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Note: For RF type 0222D
|
||||
*---------------------------------------------------------------------------*/
|
||||
void rtl8188e_PHY_RF6052SetBandwidth(struct adapter *Adapter,
|
||||
enum ht_channel_width Bandwidth)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
switch (Bandwidth) {
|
||||
case HT_CHANNEL_WIDTH_20:
|
||||
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10) | BIT(11));
|
||||
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
|
||||
break;
|
||||
case HT_CHANNEL_WIDTH_40:
|
||||
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT(10));
|
||||
PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: PHY_RF6052SetCckTxPower
|
||||
*
|
||||
* Overview:
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/05/2008 MHC Simulate 8192series..
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
void
|
||||
rtl8188e_PHY_RF6052SetCckTxPower(
|
||||
struct adapter *Adapter,
|
||||
u8 *pPowerlevel)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
|
||||
u32 TxAGC[2] = {0, 0}, tmpval = 0, pwrtrac_value;
|
||||
bool TurboScanOff = false;
|
||||
u8 idx1, idx2;
|
||||
u8 *ptr;
|
||||
u8 direction;
|
||||
/* FOR CE ,must disable turbo scan */
|
||||
TurboScanOff = true;
|
||||
|
||||
|
||||
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
|
||||
TxAGC[RF_PATH_A] = 0x3f3f3f3f;
|
||||
TxAGC[RF_PATH_B] = 0x3f3f3f3f;
|
||||
|
||||
TurboScanOff = true;/* disable turbo scan */
|
||||
|
||||
if (TurboScanOff) {
|
||||
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
|
||||
TxAGC[idx1] =
|
||||
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
|
||||
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
|
||||
/* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */
|
||||
if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
|
||||
TxAGC[idx1] = 0x20;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* Driver dynamic Tx power shall not affect Tx power.
|
||||
* It shall be determined by power training mechanism.
|
||||
i * Currently, we cannot fully disable driver dynamic
|
||||
* tx power mechanism because it is referenced by BT
|
||||
* coexist mechanism.
|
||||
* In the future, two mechanism shall be separated from
|
||||
* each other and maintained independantly. */
|
||||
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
|
||||
TxAGC[RF_PATH_A] = 0x10101010;
|
||||
TxAGC[RF_PATH_B] = 0x10101010;
|
||||
} else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
|
||||
TxAGC[RF_PATH_A] = 0x00000000;
|
||||
TxAGC[RF_PATH_B] = 0x00000000;
|
||||
} else {
|
||||
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
|
||||
TxAGC[idx1] =
|
||||
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
|
||||
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
|
||||
}
|
||||
if (pHalData->EEPROMRegulatory == 0) {
|
||||
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
|
||||
(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
|
||||
TxAGC[RF_PATH_A] += tmpval;
|
||||
|
||||
tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
|
||||
(pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
|
||||
TxAGC[RF_PATH_B] += tmpval;
|
||||
}
|
||||
}
|
||||
}
|
||||
for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
|
||||
ptr = (u8 *)(&(TxAGC[idx1]));
|
||||
for (idx2 = 0; idx2 < 4; idx2++) {
|
||||
if (*ptr > RF6052_MAX_TX_PWR)
|
||||
*ptr = RF6052_MAX_TX_PWR;
|
||||
ptr++;
|
||||
}
|
||||
}
|
||||
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value);
|
||||
|
||||
if (direction == 1) {
|
||||
/* Increase TX pwoer */
|
||||
TxAGC[0] += pwrtrac_value;
|
||||
TxAGC[1] += pwrtrac_value;
|
||||
} else if (direction == 2) {
|
||||
/* Decrease TX pwoer */
|
||||
TxAGC[0] -= pwrtrac_value;
|
||||
TxAGC[1] -= pwrtrac_value;
|
||||
}
|
||||
|
||||
/* rf-A cck tx power */
|
||||
tmpval = TxAGC[RF_PATH_A]&0xff;
|
||||
PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
|
||||
tmpval = TxAGC[RF_PATH_A]>>8;
|
||||
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
|
||||
|
||||
/* rf-B cck tx power */
|
||||
tmpval = TxAGC[RF_PATH_B]>>24;
|
||||
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
|
||||
tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
|
||||
PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
|
||||
} /* PHY_RF6052SetCckTxPower */
|
||||
|
||||
/* */
|
||||
/* powerbase0 for OFDM rates */
|
||||
/* powerbase1 for HT MCS rates */
|
||||
/* */
|
||||
static void getpowerbase88e(struct adapter *Adapter, u8 *pPowerLevelOFDM,
|
||||
u8 *pPowerLevelBW20, u8 *pPowerLevelBW40, u8 Channel, u32 *OfdmBase, u32 *MCSBase)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
u32 powerBase0, powerBase1;
|
||||
u8 i, powerlevel[2];
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
powerBase0 = pPowerLevelOFDM[i];
|
||||
|
||||
powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
|
||||
*(OfdmBase+i) = powerBase0;
|
||||
}
|
||||
for (i = 0; i < pHalData->NumTotalRFPath; i++) {
|
||||
/* Check HT20 to HT40 diff */
|
||||
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
|
||||
powerlevel[i] = pPowerLevelBW20[i];
|
||||
else
|
||||
powerlevel[i] = pPowerLevelBW40[i];
|
||||
powerBase1 = powerlevel[i];
|
||||
powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
|
||||
*(MCSBase+i) = powerBase1;
|
||||
}
|
||||
}
|
||||
static void get_rx_power_val_by_reg(struct adapter *Adapter, u8 Channel,
|
||||
u8 index, u32 *powerBase0, u32 *powerBase1,
|
||||
u32 *pOutWriteVal)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
u8 i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
|
||||
s8 pwr_diff = 0;
|
||||
u32 writeVal, customer_limit, rf;
|
||||
u8 Regulatory = pHalData->EEPROMRegulatory;
|
||||
|
||||
/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
|
||||
|
||||
for (rf = 0; rf < 2; rf++) {
|
||||
switch (Regulatory) {
|
||||
case 0: /* Realtek better performance */
|
||||
/* increase power diff defined by Realtek for large power */
|
||||
chnlGroup = 0;
|
||||
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
|
||||
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
|
||||
break;
|
||||
case 1: /* Realtek regulatory */
|
||||
/* increase power diff defined by Realtek for regulatory */
|
||||
if (pHalData->pwrGroupCnt == 1)
|
||||
chnlGroup = 0;
|
||||
if (pHalData->pwrGroupCnt >= pHalData->PGMaxGroup) {
|
||||
if (Channel < 3) /* Chanel 1-2 */
|
||||
chnlGroup = 0;
|
||||
else if (Channel < 6) /* Channel 3-5 */
|
||||
chnlGroup = 1;
|
||||
else if (Channel < 9) /* Channel 6-8 */
|
||||
chnlGroup = 2;
|
||||
else if (Channel < 12) /* Channel 9-11 */
|
||||
chnlGroup = 3;
|
||||
else if (Channel < 14) /* Channel 12-13 */
|
||||
chnlGroup = 4;
|
||||
else if (Channel == 14) /* Channel 14 */
|
||||
chnlGroup = 5;
|
||||
}
|
||||
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
|
||||
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
|
||||
break;
|
||||
case 2: /* Better regulatory */
|
||||
/* don't increase any power diff */
|
||||
writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
|
||||
break;
|
||||
case 3: /* Customer defined power diff. */
|
||||
/* increase power diff defined by customer. */
|
||||
chnlGroup = 0;
|
||||
|
||||
if (index < 2)
|
||||
pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
|
||||
else if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
|
||||
pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
|
||||
|
||||
if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
|
||||
customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
|
||||
else
|
||||
customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
|
||||
|
||||
if (pwr_diff >= customer_pwr_limit)
|
||||
pwr_diff = 0;
|
||||
else
|
||||
pwr_diff = customer_pwr_limit - pwr_diff;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)]&(0x7f<<(i*8)))>>(i*8));
|
||||
|
||||
if (pwr_diff_limit[i] > pwr_diff)
|
||||
pwr_diff_limit[i] = pwr_diff;
|
||||
}
|
||||
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
|
||||
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
|
||||
writeVal = customer_limit + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
|
||||
break;
|
||||
default:
|
||||
chnlGroup = 0;
|
||||
writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf ? 8 : 0)] +
|
||||
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
|
||||
break;
|
||||
}
|
||||
/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
|
||||
/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
|
||||
/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */
|
||||
/* 92d do not need this */
|
||||
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
|
||||
writeVal = 0x14141414;
|
||||
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
|
||||
writeVal = 0x00000000;
|
||||
|
||||
/* 20100628 Joseph: High power mode for BT-Coexist mechanism. */
|
||||
/* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */
|
||||
if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
|
||||
writeVal = writeVal - 0x06060606;
|
||||
else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
|
||||
writeVal = writeVal;
|
||||
*(pOutWriteVal+rf) = writeVal;
|
||||
}
|
||||
}
|
||||
static void writeOFDMPowerReg88E(struct adapter *Adapter, u8 index, u32 *pValue)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
u16 regoffset_a[6] = {
|
||||
rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
|
||||
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
|
||||
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
|
||||
u16 regoffset_b[6] = {
|
||||
rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
|
||||
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
|
||||
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
|
||||
u8 i, rf, pwr_val[4];
|
||||
u32 writeVal;
|
||||
u16 regoffset;
|
||||
|
||||
for (rf = 0; rf < 2; rf++) {
|
||||
writeVal = pValue[rf];
|
||||
for (i = 0; i < 4; i++) {
|
||||
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
|
||||
if (pwr_val[i] > RF6052_MAX_TX_PWR)
|
||||
pwr_val[i] = RF6052_MAX_TX_PWR;
|
||||
}
|
||||
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | (pwr_val[1]<<8) | pwr_val[0];
|
||||
|
||||
if (rf == 0)
|
||||
regoffset = regoffset_a[index];
|
||||
else
|
||||
regoffset = regoffset_b[index];
|
||||
|
||||
PHY_SetBBReg(Adapter, regoffset, bMaskDWord, writeVal);
|
||||
|
||||
/* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */
|
||||
if (((pHalData->rf_type == RF_2T2R) &&
|
||||
(regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs15_Mcs12)) ||
|
||||
((pHalData->rf_type != RF_2T2R) &&
|
||||
(regoffset == rTxAGC_A_Mcs07_Mcs04 || regoffset == rTxAGC_B_Mcs07_Mcs04))) {
|
||||
writeVal = pwr_val[3];
|
||||
if (regoffset == rTxAGC_A_Mcs15_Mcs12 || regoffset == rTxAGC_A_Mcs07_Mcs04)
|
||||
regoffset = 0xc90;
|
||||
if (regoffset == rTxAGC_B_Mcs15_Mcs12 || regoffset == rTxAGC_B_Mcs07_Mcs04)
|
||||
regoffset = 0xc98;
|
||||
for (i = 0; i < 3; i++) {
|
||||
if (i != 2)
|
||||
writeVal = (writeVal > 8) ? (writeVal-8) : 0;
|
||||
else
|
||||
writeVal = (writeVal > 6) ? (writeVal-6) : 0;
|
||||
rtw_write8(Adapter, (u32)(regoffset+i), (u8)writeVal);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: PHY_RF6052SetOFDMTxPower
|
||||
*
|
||||
* Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
|
||||
* different channel and read original value in TX power register area from
|
||||
* 0xe00. We increase offset and original value to be correct tx pwr.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/05/2008 MHC Simulate 8192 series method.
|
||||
* 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
|
||||
* A/B pwr difference or legacy/HT pwr diff.
|
||||
* 2. We concern with path B legacy/HT OFDM difference.
|
||||
* 01/22/2009 MHC Support new EPRO format from SD3.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
void
|
||||
rtl8188e_PHY_RF6052SetOFDMTxPower(
|
||||
struct adapter *Adapter,
|
||||
u8 *pPowerLevelOFDM,
|
||||
u8 *pPowerLevelBW20,
|
||||
u8 *pPowerLevelBW40,
|
||||
u8 Channel)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
|
||||
u8 direction;
|
||||
u8 index = 0;
|
||||
|
||||
getpowerbase88e(Adapter, pPowerLevelOFDM, pPowerLevelBW20, pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
|
||||
|
||||
/* 2012/04/23 MH According to power tracking value, we need to revise OFDM tx power. */
|
||||
/* This is ued to fix unstable power tracking mode. */
|
||||
ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 0, &direction, &pwrtrac_value);
|
||||
|
||||
for (index = 0; index < 6; index++) {
|
||||
get_rx_power_val_by_reg(Adapter, Channel, index,
|
||||
&powerBase0[0], &powerBase1[0],
|
||||
&writeVal[0]);
|
||||
|
||||
if (direction == 1) {
|
||||
writeVal[0] += pwrtrac_value;
|
||||
writeVal[1] += pwrtrac_value;
|
||||
} else if (direction == 2) {
|
||||
writeVal[0] -= pwrtrac_value;
|
||||
writeVal[1] -= pwrtrac_value;
|
||||
}
|
||||
writeOFDMPowerReg88E(Adapter, index, &writeVal[0]);
|
||||
}
|
||||
}
|
||||
|
||||
static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
|
||||
{
|
||||
struct bb_reg_def *pPhyReg;
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
u32 u4RegValue = 0;
|
||||
u8 eRFPath;
|
||||
int rtStatus = _SUCCESS;
|
||||
|
||||
/* 3----------------------------------------------------------------- */
|
||||
/* 3 <2> Initialize RF */
|
||||
/* 3----------------------------------------------------------------- */
|
||||
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
|
||||
pPhyReg = &pHalData->PHYRegDef[eRFPath];
|
||||
|
||||
/*----Store original RFENV control type----*/
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
case RF_PATH_C:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
case RF_PATH_D:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
|
||||
break;
|
||||
}
|
||||
/*----Set RF_ENV enable----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Set RF_ENV output high----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/* Set bit number of Address and Data for RF register */
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
|
||||
rtw_udelay_os(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Initialize RF fom connfiguration file----*/
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
||||
rtStatus = _FAIL;
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum ODM_RF_RADIO_PATH)eRFPath, (enum ODM_RF_RADIO_PATH)eRFPath))
|
||||
rtStatus = _FAIL;
|
||||
break;
|
||||
case RF_PATH_C:
|
||||
break;
|
||||
case RF_PATH_D:
|
||||
break;
|
||||
}
|
||||
/*----Restore RFENV control type----*/;
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
case RF_PATH_C:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
case RF_PATH_D:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
|
||||
break;
|
||||
}
|
||||
if (rtStatus != _SUCCESS)
|
||||
goto phy_RF6052_Config_ParaFile_Fail;
|
||||
}
|
||||
return rtStatus;
|
||||
|
||||
phy_RF6052_Config_ParaFile_Fail:
|
||||
return rtStatus;
|
||||
}
|
||||
|
||||
int PHY_RF6052_Config8188E(struct adapter *Adapter)
|
||||
{
|
||||
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
|
||||
int rtStatus = _SUCCESS;
|
||||
|
||||
/* */
|
||||
/* Initialize general global value */
|
||||
/* */
|
||||
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
|
||||
if (pHalData->rf_type == RF_1T1R)
|
||||
pHalData->NumTotalRFPath = 1;
|
||||
else
|
||||
pHalData->NumTotalRFPath = 2;
|
||||
|
||||
/* */
|
||||
/* Config BB and RF */
|
||||
/* */
|
||||
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
|
||||
return rtStatus;
|
||||
}
|
||||
Reference in New Issue
Block a user