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drm/msm/registers: Generate _HI/LO builders for reg64

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The upstream mesa copy of the GPU regs has shifted more things to reg64
instead of seperate 32b HI/LO reg32's.  This works better with the "new-
style" c++ builders that mesa has been migrating to for a6xx+ (to better
handle register shuffling between gens), but it leaves the C builders
with missing _HI/LO builders.

So handle the special case of reg64, automatically generating the
missing _HI/LO builders.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673559/
This commit is contained in:
Rob Clark
2025-09-08 12:30:07 -07:00
parent 29e087f31b
commit 60e9f776b7
1 changed files with 7 additions and 0 deletions
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7
drivers/gpu/drm/msm/registers/gen_header.py
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@@ -161,6 +161,7 @@ class Bitset(object):
def __init__(self, name, template):
self.name = name
self.inline = False
self.reg = None
if template:
self.fields = template.fields[:]
else:
@@ -266,6 +267,11 @@ class Bitset(object):
def dump(self, is_deprecated, prefix=None):
if prefix is None:
prefix = self.name
if self.reg and self.reg.bit_size == 64:
print("static inline uint32_t %s_LO(uint32_t val)\n{" % prefix)
print("\treturn val;\n}")
print("static inline uint32_t %s_HI(uint32_t val)\n{" % prefix)
print("\treturn val;\n}")
for f in self.fields:
if f.name:
name = prefix + "_" + f.name
@@ -645,6 +651,7 @@ class Parser(object):
self.current_reg = Reg(attrs, self.prefix(variant), self.current_array, bit_size)
self.current_reg.bitset = self.current_bitset
self.current_bitset.reg = self.current_reg
if len(self.stack) == 1:
self.file.append(self.current_reg)