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drm/msm/dpu: inline _setup_ctl_ops()

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Inline the _setup_ctl_ops() function, it makes it easier to handle
different conditions involving CTL configuration.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655367/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-3-3b2085a07884@oss.qualcomm.com
This commit is contained in:
Dmitry Baryshkov
2025-05-22 22:03:22 +03:00
committed by Dmitry Baryshkov
parent 9375fb3ebd
commit 60bd327651
1 changed files with 47 additions and 51 deletions
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98
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
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@@ -737,56 +737,6 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
}
static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
unsigned long cap)
{
if (cap & BIT(DPU_CTL_ACTIVE_CFG)) {
ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1;
ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
ops->update_pending_flush_intf =
dpu_hw_ctl_update_pending_flush_intf_v1;
ops->update_pending_flush_periph =
dpu_hw_ctl_update_pending_flush_periph_v1;
ops->update_pending_flush_merge_3d =
dpu_hw_ctl_update_pending_flush_merge_3d_v1;
ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;
ops->update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1;
ops->update_pending_flush_dsc =
dpu_hw_ctl_update_pending_flush_dsc_v1;
ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;
} else {
ops->trigger_flush = dpu_hw_ctl_trigger_flush;
ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
ops->update_pending_flush_intf =
dpu_hw_ctl_update_pending_flush_intf;
ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;
ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;
}
ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
ops->update_pending_flush = dpu_hw_ctl_update_pending_flush;
ops->get_pending_flush = dpu_hw_ctl_get_pending_flush;
ops->get_flush_register = dpu_hw_ctl_get_flush_register;
ops->trigger_start = dpu_hw_ctl_trigger_start;
ops->is_started = dpu_hw_ctl_is_started;
ops->trigger_pending = dpu_hw_ctl_trigger_pending;
ops->reset = dpu_hw_ctl_reset_control;
ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
else
ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
if (cap & BIT(DPU_CTL_FETCH_ACTIVE))
ops->set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
};
/**
* dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.
* Should be called before accessing any ctl_path register.
@@ -812,7 +762,53 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
c->hw.log_mask = DPU_DBG_MASK_CTL;
c->caps = cfg;
_setup_ctl_ops(&c->ops, c->caps->features);
if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
c->ops.update_pending_flush_intf =
dpu_hw_ctl_update_pending_flush_intf_v1;
c->ops.update_pending_flush_periph =
dpu_hw_ctl_update_pending_flush_periph_v1;
c->ops.update_pending_flush_merge_3d =
dpu_hw_ctl_update_pending_flush_merge_3d_v1;
c->ops.update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;
c->ops.update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1;
c->ops.update_pending_flush_dsc =
dpu_hw_ctl_update_pending_flush_dsc_v1;
c->ops.update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;
} else {
c->ops.trigger_flush = dpu_hw_ctl_trigger_flush;
c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg;
c->ops.update_pending_flush_intf =
dpu_hw_ctl_update_pending_flush_intf;
c->ops.update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;
c->ops.update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;
}
c->ops.clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
c->ops.update_pending_flush = dpu_hw_ctl_update_pending_flush;
c->ops.get_pending_flush = dpu_hw_ctl_get_pending_flush;
c->ops.get_flush_register = dpu_hw_ctl_get_flush_register;
c->ops.trigger_start = dpu_hw_ctl_trigger_start;
c->ops.is_started = dpu_hw_ctl_is_started;
c->ops.trigger_pending = dpu_hw_ctl_trigger_pending;
c->ops.reset = dpu_hw_ctl_reset_control;
c->ops.wait_reset_status = dpu_hw_ctl_wait_reset_status;
c->ops.clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
else
c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE))
c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
c->idx = cfg->id;
c->mixer_count = mixer_count;
c->mixer_hw_caps = mixer;