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drm/i915: Bump RING_FAULT engine ID bits

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The fault engine ID field has been 5 bits since icl. Bump our
define to match. The extra bits were unused before icl so we
should be able to use the larger mask unconditionally.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-2-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
2025-02-12 01:19:29 +02:00
committed by Andi Shyti
parent 7ded94bd11
commit 600a0c7e76
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/gt/intel_gt_regs.h
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@@ -1044,7 +1044,7 @@
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
#define XELPMP_RING_FAULT_REG _MMIO(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)