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dt-bindings: clock: ti: Convert mux.txt to json-schema

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Convert the OMAP mux clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
Choose GPL-only license because original binding was also GPL.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241112162618.400194-1-andreas@kemnade.info
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Andreas Kemnade
2024-11-12 17:26:18 +01:00
committed by Stephen Boyd
parent 0fcd58492f
commit 5fbe6f51ca
3 changed files with 126 additions and 79 deletions
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2
Documentation/devicetree/bindings/clock/ti/composite.txt
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@@ -16,7 +16,7 @@ merged to this clock. The component clocks shall be of one of the
"ti,*composite*-clock" types.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/mux.txt
[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
[4] Documentation/devicetree/bindings/clock/ti/gate.txt

78
Documentation/devicetree/bindings/clock/ti/mux.txt
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@@ -1,78 +0,0 @@
Binding for TI mux clock.
This binding uses the common clock binding[1]. It assumes a
register-mapped multiplexer with multiple input clock signals or
parents, one of which can be selected as output. This clock does not
gate or adjust the parent rate via a divider or multiplier.
By default the "clocks" property lists the parents in the same order
as they are programmed into the register. E.g:
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
results in programming the register as follows:
register value selected parent clock
0 foo_clock
1 bar_clock
2 baz_clock
Some clock controller IPs do not allow a value of zero to be programmed
into the register, instead indexing begins at 1. The optional property
"index-starts-at-one" modified the scheme as follows:
register value selected clock parent
1 foo_clock
2 bar_clock
3 baz_clock
The binding must provide the register to control the mux. Optionally
the number of bits to shift the control field in the register can be
supplied. If the shift value is missing it is the same as supplying
a zero shift.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks
- reg : register offset for register controlling adjustable mux
Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
0 if not present
- ti,index-starts-at-one : valid input select programming starts at 1, not
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
- ti,latch-bit : latch the mux value to HW, only needed if the register
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
implements such behavior.
Examples:
sys_clkin_ck: sys_clkin_ck@4a306110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
reg = <0x0110>;
ti,index-starts-at-one;
};
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
ti,bit-shift = <24>;
reg = <0x0108>;
};
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02d8>;
};

125
Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml Normal file
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@@ -0,0 +1,125 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments mux clock
maintainers:
- Tero Kristo <kristo@kernel.org>
description: |
This clock assumes a register-mapped multiplexer with multiple inpt clock
signals or parents, one of which can be selected as output. This clock does
not gate or adjust the parent rate via a divider or multiplier.
By default the "clocks" property lists the parents in the same order
as they are programmed into the register. E.g:
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
Results in programming the register as follows:
register value selected parent clock
0 foo_clock
1 bar_clock
2 baz_clock
Some clock controller IPs do not allow a value of zero to be programmed
into the register, instead indexing begins at 1. The optional property
"index-starts-at-one" modified the scheme as follows:
register value selected clock parent
1 foo_clock
2 bar_clock
3 baz_clock
The binding must provide the register to control the mux. Optionally
the number of bits to shift the control field in the register can be
supplied. If the shift value is missing it is the same as supplying
a zero shift.
properties:
compatible:
enum:
- ti,mux-clock
- ti,composite-mux-clock
"#clock-cells":
const: 0
clocks: true
clock-output-names:
maxItems: 1
reg:
maxItems: 1
ti,bit-shift:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of bits to shift the bit-mask
maximum: 31
default: 0
ti,index-starts-at-one:
type: boolean
description:
Valid input select programming starts at 1, not zero
ti,set-rate-parent:
type: boolean
description:
clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype.
ti,latch-bit:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Latch the mux value to HW, only needed if the register
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
implements such behavior.
maximum: 31
if:
properties:
compatible:
contains:
const: ti,composite-mux-clock
then:
properties:
ti,set-rate-parent: false
required:
- compatible
- "#clock-cells"
- clocks
- reg
additionalProperties: false
examples:
- |
bus {
#address-cells = <1>;
#size-cells = <0>;
clock-controller@110 {
compatible = "ti,mux-clock";
reg = <0x0110>;
#clock-cells = <0>;
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>;
ti,index-starts-at-one;
ti,set-rate-parent;
};
clock-controller@120 {
compatible = "ti,composite-mux-clock";
reg = <0x0120>;
#clock-cells = <0>;
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
};
};