drm/amd/display: augment display clock in dc_cap structure

[Why]
Allow dc report maximum display clock possible at vmin

Reviewed-by: Wayne Lin <wayne.lin@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Max Tseng <max.tseng@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Max Tseng
2023-09-08 15:31:33 +08:00
committed by Alex Deucher
parent b308e6f3af
commit 5fad7d8cc4
3 changed files with 5 additions and 0 deletions

View File

@@ -270,6 +270,7 @@ struct dc_caps {
uint16_t subvp_vertical_int_margin_us;
bool seamless_odm;
uint32_t max_v_total;
uint32_t max_disp_clock_khz_at_vmin;
uint8_t subvp_drr_vblank_start_margin_us;
};

View File

@@ -1914,6 +1914,8 @@ static bool dcn314_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.max_disp_clock_khz_at_vmin = 694000;
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;

View File

@@ -1832,6 +1832,8 @@ static bool dcn35_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.max_disp_clock_khz_at_vmin = 669154;
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;
/* read VBIOS LTTPR caps */