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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-24 08:00:55 -04:00
drm/ast: Store register addresses in struct ast_dramstruct
Struct ast_dramstruct contains a 16-bit index field that either contains a magic value or serves as index into the P2A address segment at 0x1e600000. This segment serves MCR and SCU registers, which the ast_dramstruct programs. It's fragile and relies upon the ast_post_chip_*() functions to set up the segment correctly. Replace the 16-bit index with a full 32-bit address of the SCU and MCR addresses. Initialize the DRAM tables with full register constants and write them out with ast_moutdwm(). This sets the correct segment on each write. Drop __AST_DRAMSTRUCT_DRAM_TYPE as it simply referred to MCR04. Use the latter for initializing the DRAM tables. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patch.msgid.link/20260327133532.79696-10-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann
@@ -69,30 +69,30 @@ void ast_2000_set_def_ext_reg(struct ast_device *ast)
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}
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static const struct ast_dramstruct ast2000_dram_table_data[] = {
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{ 0x0108, 0x00000000 },
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{ 0x0120, 0x00004a21 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR108, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR120, 0x00004a21),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x0000, 0xFFFFFFFF },
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AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000089),
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{ 0x0008, 0x22331353 },
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{ 0x000C, 0x0d07000b },
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{ 0x0010, 0x11113333 },
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{ 0x0020, 0x00110350 },
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{ 0x0028, 0x1e0828f0 },
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{ 0x0024, 0x00000001 },
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{ 0x001C, 0x00000000 },
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{ 0x0014, 0x00000003 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR00, 0xffffffff), /* FIXME: This locks the MCR registers. */
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AST_DRAMSTRUCT_REG(AST_REG_MCR04, 0x00000089), /* DRAM type */
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AST_DRAMSTRUCT_REG(AST_REG_MCR08, 0x22331353),
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AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x0d07000b),
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AST_DRAMSTRUCT_REG(AST_REG_MCR10, 0x11113333),
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AST_DRAMSTRUCT_REG(AST_REG_MCR20, 0x00110350),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x1e0828f0),
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AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00000001),
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AST_DRAMSTRUCT_REG(AST_REG_MCR1C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000003),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x0018, 0x00000131 },
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{ 0x0014, 0x00000001 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x00000131),
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AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000001),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x0018, 0x00000031 },
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{ 0x0014, 0x00000001 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x00000031),
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AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x00000001),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x0028, 0x1e0828f1 },
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{ 0x0024, 0x00000003 },
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{ 0x002C, 0x1f0f28fb },
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{ 0x0030, 0xFFFFFE01 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x1e0828f1),
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AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00000003),
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AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x1f0f28fb),
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AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0xfffffe01),
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AST_DRAMSTRUCT_INVALID,
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};
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@@ -119,8 +119,7 @@ static void ast_post_chip_2000(struct ast_device *ast)
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for (i = 0; i < 15; i++)
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udelay(dram_reg_info->data);
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} else {
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ast_write32(ast, 0x10000 + dram_reg_info->index,
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dram_reg_info->data);
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ast_moutdwm(ast, dram_reg_info->index, dram_reg_info->data);
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}
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dram_reg_info++;
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}
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@@ -72,108 +72,108 @@ static enum ast_dram_layout ast_2100_get_dram_layout_p2a(struct ast_device *ast)
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*/
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static const struct ast_dramstruct ast1100_dram_table_data[] = {
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{ 0x2000, 0x1688a8a8 },
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{ 0x2020, 0x000041f0 },
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AST_DRAMSTRUCT_REG(AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY),
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AST_DRAMSTRUCT_REG(AST_REG_SCU020, 0x000041f0),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x0000, 0xfc600309 },
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{ 0x006C, 0x00909090 },
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{ 0x0064, 0x00050000 },
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AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000585),
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{ 0x0008, 0x0011030f },
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{ 0x0010, 0x22201724 },
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{ 0x0018, 0x1e29011a },
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{ 0x0020, 0x00c82222 },
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{ 0x0014, 0x01001523 },
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{ 0x001C, 0x1024010d },
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{ 0x0024, 0x00cb2522 },
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{ 0x0038, 0xffffff82 },
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{ 0x003C, 0x00000000 },
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{ 0x0040, 0x00000000 },
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{ 0x0044, 0x00000000 },
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{ 0x0048, 0x00000000 },
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{ 0x004C, 0x00000000 },
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{ 0x0050, 0x00000000 },
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{ 0x0054, 0x00000000 },
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{ 0x0058, 0x00000000 },
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{ 0x005C, 0x00000000 },
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{ 0x0060, 0x032aa02a },
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{ 0x0064, 0x002d3000 },
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{ 0x0068, 0x00000000 },
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{ 0x0070, 0x00000000 },
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{ 0x0074, 0x00000000 },
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{ 0x0078, 0x00000000 },
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{ 0x007C, 0x00000000 },
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{ 0x0034, 0x00000001 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY),
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AST_DRAMSTRUCT_REG(AST_REG_MCR6C, 0x00909090),
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AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x00050000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR04, 0x00000585), // DRAM type
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AST_DRAMSTRUCT_REG(AST_REG_MCR08, 0x0011030f),
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AST_DRAMSTRUCT_REG(AST_REG_MCR10, 0x22201724),
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AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x1e29011a),
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AST_DRAMSTRUCT_REG(AST_REG_MCR20, 0x00c82222),
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AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x01001523),
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AST_DRAMSTRUCT_REG(AST_REG_MCR1C, 0x1024010d),
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AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00cb2522),
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AST_DRAMSTRUCT_REG(AST_REG_MCR38, 0xffffff82),
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AST_DRAMSTRUCT_REG(AST_REG_MCR3C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR40, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR44, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR48, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR4C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR50, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR54, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR58, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR5C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR60, 0x032aa02a),
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AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x002d3000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR68, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR70, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR74, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR78, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR7C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00000001),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x002C, 0x00000732 },
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{ 0x0030, 0x00000040 },
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{ 0x0028, 0x00000005 },
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{ 0x0028, 0x00000007 },
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{ 0x0028, 0x00000003 },
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{ 0x0028, 0x00000001 },
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{ 0x000C, 0x00005a08 },
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{ 0x002C, 0x00000632 },
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{ 0x0028, 0x00000001 },
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{ 0x0030, 0x000003c0 },
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{ 0x0028, 0x00000003 },
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{ 0x0030, 0x00000040 },
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{ 0x0028, 0x00000003 },
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{ 0x000C, 0x00005a21 },
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{ 0x0034, 0x00007c03 },
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{ 0x0120, 0x00004c41 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000732),
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AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000005),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000007),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001),
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AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a08),
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AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000632),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001),
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AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x000003c0),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003),
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AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003),
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AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a21),
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AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00007c03),
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AST_DRAMSTRUCT_REG(AST_REG_MCR120, 0x00004c41),
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AST_DRAMSTRUCT_INVALID,
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};
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static const struct ast_dramstruct ast2100_dram_table_data[] = {
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{ 0x2000, 0x1688a8a8 },
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{ 0x2020, 0x00004120 },
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AST_DRAMSTRUCT_REG(AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY),
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AST_DRAMSTRUCT_REG(AST_REG_SCU020, 0x00004120),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x0000, 0xfc600309 },
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{ 0x006C, 0x00909090 },
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{ 0x0064, 0x00070000 },
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AST_DRAMSTRUCT_INIT(DRAM_TYPE, 0x00000489),
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{ 0x0008, 0x0011030f },
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{ 0x0010, 0x32302926 },
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{ 0x0018, 0x274c0122 },
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{ 0x0020, 0x00ce2222 },
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{ 0x0014, 0x01001523 },
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{ 0x001C, 0x1024010d },
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{ 0x0024, 0x00cb2522 },
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{ 0x0038, 0xffffff82 },
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{ 0x003C, 0x00000000 },
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{ 0x0040, 0x00000000 },
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{ 0x0044, 0x00000000 },
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{ 0x0048, 0x00000000 },
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{ 0x004C, 0x00000000 },
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{ 0x0050, 0x00000000 },
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{ 0x0054, 0x00000000 },
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{ 0x0058, 0x00000000 },
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{ 0x005C, 0x00000000 },
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{ 0x0060, 0x0f2aa02a },
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{ 0x0064, 0x003f3005 },
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{ 0x0068, 0x02020202 },
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{ 0x0070, 0x00000000 },
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{ 0x0074, 0x00000000 },
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{ 0x0078, 0x00000000 },
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{ 0x007C, 0x00000000 },
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{ 0x0034, 0x00000001 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY),
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AST_DRAMSTRUCT_REG(AST_REG_MCR6C, 0x00909090),
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AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x00070000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR04, 0x00000489), // DRAM type
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AST_DRAMSTRUCT_REG(AST_REG_MCR08, 0x0011030f),
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AST_DRAMSTRUCT_REG(AST_REG_MCR10, 0x32302926),
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AST_DRAMSTRUCT_REG(AST_REG_MCR18, 0x274c0122),
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AST_DRAMSTRUCT_REG(AST_REG_MCR20, 0x00ce2222),
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AST_DRAMSTRUCT_REG(AST_REG_MCR14, 0x01001523),
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AST_DRAMSTRUCT_REG(AST_REG_MCR1C, 0x1024010d),
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AST_DRAMSTRUCT_REG(AST_REG_MCR24, 0x00cb2522),
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AST_DRAMSTRUCT_REG(AST_REG_MCR38, 0xffffff82),
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AST_DRAMSTRUCT_REG(AST_REG_MCR3C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR40, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR44, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR48, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR4C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR50, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR54, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR58, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR5C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR60, 0x0f2aa02a),
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AST_DRAMSTRUCT_REG(AST_REG_MCR64, 0x003f3005),
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AST_DRAMSTRUCT_REG(AST_REG_MCR68, 0x02020202),
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AST_DRAMSTRUCT_REG(AST_REG_MCR70, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR74, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR78, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR7C, 0x00000000),
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AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00000001),
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AST_DRAMSTRUCT_UDELAY(67u),
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{ 0x002C, 0x00000942 },
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{ 0x0030, 0x00000040 },
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{ 0x0028, 0x00000005 },
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{ 0x0028, 0x00000007 },
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{ 0x0028, 0x00000003 },
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{ 0x0028, 0x00000001 },
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{ 0x000C, 0x00005a08 },
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{ 0x002C, 0x00000842 },
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{ 0x0028, 0x00000001 },
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{ 0x0030, 0x000003c0 },
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{ 0x0028, 0x00000003 },
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{ 0x0030, 0x00000040 },
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{ 0x0028, 0x00000003 },
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{ 0x000C, 0x00005a21 },
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{ 0x0034, 0x00007c03 },
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{ 0x0120, 0x00005061 },
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AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000942),
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AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000005),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000007),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001),
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AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a08),
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AST_DRAMSTRUCT_REG(AST_REG_MCR2C, 0x00000842),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000001),
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AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x000003c0),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003),
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AST_DRAMSTRUCT_REG(AST_REG_MCR30, 0x00000040),
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AST_DRAMSTRUCT_REG(AST_REG_MCR28, 0x00000003),
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AST_DRAMSTRUCT_REG(AST_REG_MCR0C, 0x00005a21),
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AST_DRAMSTRUCT_REG(AST_REG_MCR34, 0x00007c03),
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AST_DRAMSTRUCT_REG(AST_REG_MCR120, 0x00005061),
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AST_DRAMSTRUCT_INVALID,
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};
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@@ -328,7 +328,7 @@ static void ast_post_chip_2100(struct ast_device *ast)
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if (AST_DRAMSTRUCT_IS(dram_reg_info, UDELAY)) {
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for (i = 0; i < 15; i++)
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udelay(dram_reg_info->data);
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} else if (AST_DRAMSTRUCT_IS(dram_reg_info, DRAM_TYPE)) {
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} else if (AST_DRAMSTRUCT_IS_REG(dram_reg_info, AST_REG_MCR04)) {
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switch (dram_layout) {
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case AST_DRAM_1Gx16:
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data = 0x00000d89;
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@@ -344,10 +344,9 @@ static void ast_post_chip_2100(struct ast_device *ast)
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temp = ast_read32(ast, 0x12070);
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temp &= 0xc;
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temp <<= 2;
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ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
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ast_moutdwm(ast, dram_reg_info->index, data | temp);
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} else {
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ast_write32(ast, 0x10000 + dram_reg_info->index,
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dram_reg_info->data);
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ast_moutdwm(ast, dram_reg_info->index, dram_reg_info->data);
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}
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dram_reg_info++;
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}
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@@ -10,13 +10,10 @@ struct ast_device;
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/* DRAM timing tables */
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struct ast_dramstruct {
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u16 index;
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u32 index;
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u32 data;
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};
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/* hardware fields */
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#define __AST_DRAMSTRUCT_DRAM_TYPE 0x0004
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/* control commands */
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#define __AST_DRAMSTRUCT_UDELAY 0xff00
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#define __AST_DRAMSTRUCT_INVALID 0xffff
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@@ -24,14 +21,18 @@ struct ast_dramstruct {
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#define __AST_DRAMSTRUCT_INDEX(_name) \
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(__AST_DRAMSTRUCT_ ## _name)
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#define AST_DRAMSTRUCT_INIT(_name, _value) \
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{ __AST_DRAMSTRUCT_INDEX(_name), (_value) }
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#define __AST_DRAMSTRUCT_INIT(_index, _value) \
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{ (_index), (_value) }
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#define AST_DRAMSTRUCT_REG(_reg, _value) \
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__AST_DRAMSTRUCT_INIT(_reg, _value)
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#define AST_DRAMSTRUCT_UDELAY(_usecs) \
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AST_DRAMSTRUCT_INIT(UDELAY, _usecs)
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__AST_DRAMSTRUCT_INIT(__AST_DRAMSTRUCT_UDELAY, _usecs)
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#define AST_DRAMSTRUCT_INVALID \
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AST_DRAMSTRUCT_INIT(INVALID, U32_MAX)
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__AST_DRAMSTRUCT_INIT(__AST_DRAMSTRUCT_INVALID, U32_MAX)
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#define AST_DRAMSTRUCT_IS_REG(_entry, _reg) \
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((_entry)->index == (_reg))
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#define AST_DRAMSTRUCT_IS(_entry, _name) \
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||||
((_entry)->index == __AST_DRAMSTRUCT_INDEX(_name))
|
||||
|
||||
|
||||
@@ -120,12 +120,15 @@
|
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#define AST_REG_MCR30 AST_REG_MCR(0x30)
|
||||
#define AST_REG_MCR34 AST_REG_MCR(0x34)
|
||||
#define AST_REG_MCR38 AST_REG_MCR(0x38)
|
||||
#define AST_REG_MCR3C AST_REG_MCR(0x3c)
|
||||
#define AST_REG_MCR40 AST_REG_MCR(0x40)
|
||||
#define AST_REG_MCR44 AST_REG_MCR(0x44)
|
||||
#define AST_REG_MCR48 AST_REG_MCR(0x48)
|
||||
#define AST_REG_MCR4C AST_REG_MCR(0x4C)
|
||||
#define AST_REG_MCR50 AST_REG_MCR(0x50)
|
||||
#define AST_REG_MCR54 AST_REG_MCR(0x54)
|
||||
#define AST_REG_MCR58 AST_REG_MCR(0x58)
|
||||
#define AST_REG_MCR5C AST_REG_MCR(0x5c)
|
||||
#define AST_REG_MCR60 AST_REG_MCR(0x60)
|
||||
#define AST_REG_MCR64 AST_REG_MCR(0x64)
|
||||
#define AST_REG_MCR68 AST_REG_MCR(0x68)
|
||||
@@ -137,6 +140,7 @@
|
||||
#define AST_REG_MCR80 AST_REG_MCR(0x80)
|
||||
#define AST_REG_MCR84 AST_REG_MCR(0x84)
|
||||
#define AST_REG_MCR88 AST_REG_MCR(0x88)
|
||||
#define AST_REG_MCR108 AST_REG_MCR(0x108)
|
||||
#define AST_REG_MCR120 AST_REG_MCR(0x120)
|
||||
#define AST_REG_MCR200 AST_REG_MCR(0x200)
|
||||
#define AST_REG_MCR204 AST_REG_MCR(0x204)
|
||||
|
||||
Reference in New Issue
Block a user