mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-07 10:24:01 -04:00
Merge tag 'topic/drm-next-nouveau-r570-2025-05-19-1' of https://gitlab.freedesktop.org/drm/kernel into drm-next
drm/nouveau: r570 and hopper/blackwell support This series implements support for booting GSP-RM firmware version 570.144, and adds support for GH100, GB10x, and GB20x GPUs. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
@@ -2137,14 +2137,17 @@ static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
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for (i = 0; i < num; i++) {
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msg.address = msgs[i].addr;
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drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
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/* Send a bare address packet to start the transaction.
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* Zero sized messages specify an address only (bare
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* address) transaction.
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*/
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msg.buffer = NULL;
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msg.size = 0;
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err = drm_dp_i2c_do_msg(aux, &msg);
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if (!aux->no_zero_sized) {
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drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
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/* Send a bare address packet to start the transaction.
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* Zero sized messages specify an address only (bare
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* address) transaction.
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*/
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msg.buffer = NULL;
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msg.size = 0;
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err = drm_dp_i2c_do_msg(aux, &msg);
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}
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/*
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* Reset msg.request in case in case it got
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@@ -2163,6 +2166,8 @@ static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
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msg.buffer = msgs[i].buf + j;
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msg.size = min(transfer_size, msgs[i].len - j);
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if (j + msg.size == msgs[i].len && aux->no_zero_sized)
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msg.request &= ~DP_AUX_I2C_MOT;
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err = drm_dp_i2c_drain_msg(aux, &msg);
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/*
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@@ -2180,15 +2185,17 @@ static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
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}
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if (err >= 0)
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err = num;
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/* Send a bare address packet to close out the transaction.
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* Zero sized messages specify an address only (bare
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* address) transaction.
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*/
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msg.request &= ~DP_AUX_I2C_MOT;
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msg.buffer = NULL;
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msg.size = 0;
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(void)drm_dp_i2c_do_msg(aux, &msg);
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if (!aux->no_zero_sized) {
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/* Send a bare address packet to close out the transaction.
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* Zero sized messages specify an address only (bare
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* address) transaction.
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*/
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msg.request &= ~DP_AUX_I2C_MOT;
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msg.buffer = NULL;
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msg.size = 0;
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(void)drm_dp_i2c_do_msg(aux, &msg);
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}
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return err;
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}
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@@ -2,6 +2,7 @@
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ccflags-y += -I $(src)/include
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ccflags-y += -I $(src)/include/nvkm
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ccflags-y += -I $(src)/nvkm
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ccflags-y += -I $(src)/nvkm/subdev/gsp
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ccflags-y += -I $(src)
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# NVKM - HW resource manager
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@@ -68,5 +69,6 @@ nouveau-y += nv17_fence.o
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nouveau-y += nv50_fence.o
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nouveau-y += nv84_fence.o
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nouveau-y += nvc0_fence.o
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nouveau-y += gv100_fence.o
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obj-$(CONFIG_DRM_NOUVEAU) += nouveau.o
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@@ -768,9 +768,7 @@ static void nv_crtc_destroy(struct drm_crtc *crtc)
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disp->image[nv_crtc->index] = NULL;
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}
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nouveau_bo_unmap(nv_crtc->cursor.nvbo);
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nouveau_bo_unpin(nv_crtc->cursor.nvbo);
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nouveau_bo_fini(nv_crtc->cursor.nvbo);
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nouveau_bo_unpin_del(&nv_crtc->cursor.nvbo);
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nvif_event_dtor(&nv_crtc->vblank);
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nvif_head_dtor(&nv_crtc->head);
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kfree(nv_crtc);
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@@ -1303,6 +1301,7 @@ nv04_crtc_vblank_handler(struct nvif_event *event, void *repv, u32 repc)
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int
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nv04_crtc_create(struct drm_device *dev, int crtc_num)
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{
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struct nouveau_cli *cli = &nouveau_drm(dev)->client;
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struct nouveau_display *disp = nouveau_display(dev);
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struct nouveau_crtc *nv_crtc;
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struct drm_plane *primary;
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@@ -1336,20 +1335,9 @@ nv04_crtc_create(struct drm_device *dev, int crtc_num)
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drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
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drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
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ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100,
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NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, NULL, NULL,
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&nv_crtc->cursor.nvbo);
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if (!ret) {
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ret = nouveau_bo_pin(nv_crtc->cursor.nvbo,
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NOUVEAU_GEM_DOMAIN_VRAM, false);
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if (!ret) {
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ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
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if (ret)
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nouveau_bo_unpin(nv_crtc->cursor.nvbo);
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}
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if (ret)
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nouveau_bo_fini(nv_crtc->cursor.nvbo);
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}
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ret = nouveau_bo_new_map(cli, NOUVEAU_GEM_DOMAIN_VRAM, 64 * 64 * 4, &nv_crtc->cursor.nvbo);
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if (ret)
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return ret;
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nv04_cursor_init(nv_crtc);
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@@ -9,11 +9,13 @@ nouveau-y += dispnv50/core907d.o
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nouveau-y += dispnv50/core917d.o
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nouveau-y += dispnv50/corec37d.o
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nouveau-y += dispnv50/corec57d.o
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nouveau-y += dispnv50/coreca7d.o
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nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crc.o
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nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crc907d.o
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nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crcc37d.o
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nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crcc57d.o
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nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crcca7d.o
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nouveau-y += dispnv50/dac507d.o
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nouveau-y += dispnv50/dac907d.o
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@@ -31,6 +33,7 @@ nouveau-y += dispnv50/head907d.o
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nouveau-y += dispnv50/head917d.o
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nouveau-y += dispnv50/headc37d.o
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nouveau-y += dispnv50/headc57d.o
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nouveau-y += dispnv50/headca7d.o
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nouveau-y += dispnv50/wimm.o
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nouveau-y += dispnv50/wimmc37b.o
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@@ -39,6 +42,7 @@ nouveau-y += dispnv50/wndw.o
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nouveau-y += dispnv50/wndwc37e.o
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nouveau-y += dispnv50/wndwc57e.o
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nouveau-y += dispnv50/wndwc67e.o
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nouveau-y += dispnv50/wndwca7e.o
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nouveau-y += dispnv50/base.o
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nouveau-y += dispnv50/base507c.o
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@@ -42,6 +42,7 @@ nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore)
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int version;
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int (*new)(struct nouveau_drm *, s32, struct nv50_core **);
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} cores[] = {
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{ GB202_DISP_CORE_CHANNEL_DMA, 0, coreca7d_new },
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{ AD102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
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{ GA102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
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{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
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@@ -7,7 +7,10 @@
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struct nv50_core {
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const struct nv50_core_func *func;
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struct nv50_disp *disp;
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struct nv50_dmac chan;
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bool assign_windows;
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};
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@@ -18,6 +21,7 @@ struct nv50_core_func {
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int (*init)(struct nv50_core *);
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void (*ntfy_init)(struct nouveau_bo *, u32 offset);
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int (*caps_init)(struct nouveau_drm *, struct nv50_disp *);
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u32 caps_class;
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int (*ntfy_wait_done)(struct nouveau_bo *, u32 offset,
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struct nvif_device *);
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int (*update)(struct nv50_core *, u32 *interlock, bool ntfy);
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@@ -70,4 +74,6 @@ int corec37d_wndw_owner(struct nv50_core *);
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extern const struct nv50_outp_func sorc37d;
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int corec57d_new(struct nouveau_drm *, s32, struct nv50_core **);
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int coreca7d_new(struct nouveau_drm *, s32, struct nv50_core **);
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#endif
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@@ -165,6 +165,7 @@ core507d_new_(const struct nv50_core_func *func, struct nouveau_drm *drm,
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if (!(core = *pcore = kzalloc(sizeof(*core), GFP_KERNEL)))
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return -ENOMEM;
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core->func = func;
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core->disp = disp;
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ret = nv50_dmac_create(drm,
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&oclass, 0, &args, sizeof(args),
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@@ -105,7 +105,7 @@ int corec37d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp)
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int ret;
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ret = nvif_object_ctor(&disp->disp->object, "dispCaps", 0,
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GV100_DISP_CAPS, NULL, 0, &disp->caps);
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disp->core->func->caps_class, NULL, 0, &disp->caps);
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if (ret) {
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NV_ERROR(drm,
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"Failed to init notifier caps region: %d\n",
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@@ -162,6 +162,7 @@ corec37d = {
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.init = corec37d_init,
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.ntfy_init = corec37d_ntfy_init,
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.caps_init = corec37d_caps_init,
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.caps_class = GV100_DISP_CAPS,
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.ntfy_wait_done = corec37d_ntfy_wait_done,
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.update = corec37d_update,
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.wndw.owner = corec37d_wndw_owner,
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@@ -22,6 +22,7 @@
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#include "core.h"
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#include "head.h"
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#include <nvif/class.h>
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#include <nvif/pushc37b.h>
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#include <nvhw/class/clc57d.h>
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@@ -63,6 +64,7 @@ corec57d = {
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.init = corec57d_init,
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.ntfy_init = corec37d_ntfy_init,
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.caps_init = corec37d_caps_init,
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.caps_class = GV100_DISP_CAPS,
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.ntfy_wait_done = corec37d_ntfy_wait_done,
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.update = corec37d_update,
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.wndw.owner = corec37d_wndw_owner,
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122
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
Normal file
122
drivers/gpu/drm/nouveau/dispnv50/coreca7d.c
Normal file
@@ -0,0 +1,122 @@
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/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "core.h"
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#include "head.h"
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#include <nvif/class.h>
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#include <nvif/pushc97b.h>
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#include <nvhw/class/clca7d.h>
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#include <nouveau_bo.h>
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static int
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coreca7d_update(struct nv50_core *core, u32 *interlock, bool ntfy)
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{
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const u64 ntfy_addr = core->disp->sync->offset + NV50_DISP_CORE_NTFY;
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const u32 ntfy_hi = upper_32_bits(ntfy_addr);
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const u32 ntfy_lo = lower_32_bits(ntfy_addr);
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struct nvif_push *push = &core->chan.push;
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int ret;
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ret = PUSH_WAIT(push, 5 + (ntfy ? 5 + 2 : 0));
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if (ret)
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return ret;
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if (ntfy) {
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PUSH_MTHD(push, NVCA7D, SET_SURFACE_ADDRESS_HI_NOTIFIER, ntfy_hi,
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SET_SURFACE_ADDRESS_LO_NOTIFIER,
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NVVAL(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, ADDRESS_LO, ntfy_lo >> 4) |
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NVDEF(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, TARGET, PHYSICAL_NVM) |
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NVDEF(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE));
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PUSH_MTHD(push, NVCA7D, SET_NOTIFIER_CONTROL,
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NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, MODE, WRITE) |
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NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));
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}
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PUSH_MTHD(push, NVCA7D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS],
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SET_WINDOW_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_WNDW]);
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PUSH_MTHD(push, NVCA7D, UPDATE,
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NVDEF(NVCA7D, UPDATE, RELEASE_ELV, TRUE) |
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NVDEF(NVCA7D, UPDATE, SPECIAL_HANDLING, NONE) |
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NVDEF(NVCA7D, UPDATE, INHIBIT_INTERRUPTS, FALSE));
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if (ntfy) {
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PUSH_MTHD(push, NVCA7D, SET_NOTIFIER_CONTROL,
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NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));
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}
|
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|
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return PUSH_KICK(push);
|
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}
|
||||
|
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static int
|
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coreca7d_init(struct nv50_core *core)
|
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{
|
||||
struct nvif_push *push = &core->chan.push;
|
||||
const u32 windows = 8, heads = 4;
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int ret, i;
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ret = PUSH_WAIT(push, windows * 6 + heads * 6);
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if (ret)
|
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return ret;
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|
||||
for (i = 0; i < windows; i++) {
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PUSH_MTHD(push, NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i),
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NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED1BPP, TRUE) |
|
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NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED2BPP, TRUE) |
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NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED4BPP, TRUE) |
|
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NVDEF(NVCA7D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED8BPP, TRUE),
|
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|
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WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(i), 0x00000000);
|
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|
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PUSH_MTHD(push, NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
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||||
NVVAL(NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS, MAX_PIXELS_FETCHED_PER_LINE, 0x7fff) |
|
||||
NVDEF(NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS, ILUT_ALLOWED, TRUE) |
|
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NVDEF(NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_SCALER_TAPS, TAPS_2) |
|
||||
NVDEF(NVCA7D, WINDOW_SET_WINDOW_USAGE_BOUNDS, UPSCALING_ALLOWED, FALSE),
|
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|
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WINDOW_SET_PHYSICAL(i), BIT(i));
|
||||
}
|
||||
|
||||
for (i = 0; i < heads; i++) {
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) |
|
||||
NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, OLUT_ALLOWED, TRUE) |
|
||||
NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_SCALER_TAPS, TAPS_2) |
|
||||
NVDEF(NVCA7D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_TILE_MASK(i), BIT(i));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, TILE_SET_TILE_SIZE(i), 0);
|
||||
}
|
||||
|
||||
core->assign_windows = true;
|
||||
return PUSH_KICK(push);
|
||||
}
|
||||
|
||||
static const struct nv50_core_func
|
||||
coreca7d = {
|
||||
.init = coreca7d_init,
|
||||
.ntfy_init = corec37d_ntfy_init,
|
||||
.caps_init = corec37d_caps_init,
|
||||
.caps_class = GB202_DISP_CAPS,
|
||||
.ntfy_wait_done = corec37d_ntfy_wait_done,
|
||||
.update = coreca7d_update,
|
||||
.wndw.owner = corec37d_wndw_owner,
|
||||
.head = &headca7d,
|
||||
.sor = &sorc37d,
|
||||
#if IS_ENABLED(CONFIG_DEBUG_FS)
|
||||
.crc = &crcca7d,
|
||||
#endif
|
||||
};
|
||||
|
||||
int
|
||||
coreca7d_new(struct nouveau_drm *drm, s32 oclass, struct nv50_core **pcore)
|
||||
{
|
||||
return core507d_new_(&coreca7d, drm, oclass, pcore);
|
||||
}
|
||||
@@ -509,6 +509,10 @@ nv50_crc_ctx_init(struct nv50_head *head, struct nvif_mmu *mmu,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* No CTXDMAs on Blackwell. */
|
||||
if (core->chan.base.user.oclass >= GB202_DISP_CORE_CHANNEL_DMA)
|
||||
return 0;
|
||||
|
||||
ret = nvif_object_ctor(&core->chan.base.user, "kmsCrcNtfyCtxDma",
|
||||
NV50_DISP_HANDLE_CRC_CTX(head, idx),
|
||||
NV_DMA_IN_MEMORY,
|
||||
|
||||
@@ -94,6 +94,7 @@ void nv50_crc_atomic_clr(struct nv50_head *);
|
||||
extern const struct nv50_crc_func crc907d;
|
||||
extern const struct nv50_crc_func crcc37d;
|
||||
extern const struct nv50_crc_func crcc57d;
|
||||
extern const struct nv50_crc_func crcca7d;
|
||||
|
||||
#else /* IS_ENABLED(CONFIG_DEBUG_FS) */
|
||||
struct nv50_crc {};
|
||||
|
||||
98
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
Normal file
98
drivers/gpu/drm/nouveau/dispnv50/crcca7d.c
Normal file
@@ -0,0 +1,98 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#include "crcc37d.h"
|
||||
#include "core.h"
|
||||
#include "head.h"
|
||||
|
||||
#include <nvif/pushc97b.h>
|
||||
|
||||
#include <nvhw/class/clca7d.h>
|
||||
|
||||
static int
|
||||
crcca7d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, ctx ? 3 : 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (ctx) {
|
||||
const u32 crc_hi = upper_32_bits(ctx->mem.addr);
|
||||
const u32 crc_lo = lower_32_bits(ctx->mem.addr);
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CRC(i), crc_hi,
|
||||
|
||||
HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ADDRESS_LO, crc_lo >> 4) |
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, TARGET, PHYSICAL_NVM) |
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, ENABLE));
|
||||
} else {
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, DISABLE));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
crcca7d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source,
|
||||
struct nv50_crc_notifier_ctx *ctx)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int primary_crc, ret;
|
||||
|
||||
if (!source) {
|
||||
ret = PUSH_WAIT(push, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i), 0);
|
||||
|
||||
return crcca7d_set_ctx(head, NULL);
|
||||
}
|
||||
|
||||
switch (source) {
|
||||
case NV50_CRC_SOURCE_TYPE_SOR:
|
||||
primary_crc = NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(or);
|
||||
break;
|
||||
case NV50_CRC_SOURCE_TYPE_SF:
|
||||
primary_crc = NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
ret = crcca7d_set_ctx(head, ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_CRC_CONTROL(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, primary_crc) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct nv50_crc_func
|
||||
crcca7d = {
|
||||
.set_src = crcca7d_set_src,
|
||||
.set_ctx = crcca7d_set_ctx,
|
||||
.get_entry = crcc37d_get_entry,
|
||||
.ctx_finished = crcc37d_ctx_finished,
|
||||
.flip_threshold = CRCC37D_FLIP_THRESHOLD,
|
||||
.num_entries = CRCC37D_MAX_ENTRIES,
|
||||
.notifier_len = sizeof(struct crcc37d_notifier),
|
||||
};
|
||||
@@ -31,6 +31,7 @@ nv50_curs_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw)
|
||||
int version;
|
||||
int (*new)(struct nouveau_drm *, int, s32, struct nv50_wndw **);
|
||||
} curses[] = {
|
||||
{ GB202_DISP_CURSOR, 0, cursc37a_new },
|
||||
{ GA102_DISP_CURSOR, 0, cursc37a_new },
|
||||
{ TU102_DISP_CURSOR, 0, cursc37a_new },
|
||||
{ GV100_DISP_CURSOR, 0, cursc37a_new },
|
||||
|
||||
@@ -279,6 +279,16 @@ nv50_dmac_create(struct nouveau_drm *drm,
|
||||
if (syncbuf < 0)
|
||||
return 0;
|
||||
|
||||
/* No CTXDMAs on Blackwell. */
|
||||
if (disp->oclass >= GB202_DISP) {
|
||||
/* "handle != NULL_HANDLE" is used to determine enable status
|
||||
* in a number of places, so fill in some fake object handles.
|
||||
*/
|
||||
dmac->sync.handle = NV50_DISP_HANDLE_SYNCBUF;
|
||||
dmac->vram.handle = NV50_DISP_HANDLE_VRAM;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
|
||||
NV_DMA_IN_MEMORY,
|
||||
&(struct nv_dma_v0) {
|
||||
@@ -2808,10 +2818,7 @@ nv50_display_destroy(struct drm_device *dev)
|
||||
nvif_object_dtor(&disp->caps);
|
||||
nv50_core_del(&disp->core);
|
||||
|
||||
nouveau_bo_unmap(disp->sync);
|
||||
if (disp->sync)
|
||||
nouveau_bo_unpin(disp->sync);
|
||||
nouveau_bo_fini(disp->sync);
|
||||
nouveau_bo_unpin_del(&disp->sync);
|
||||
|
||||
nouveau_display(dev)->priv = NULL;
|
||||
kfree(disp);
|
||||
@@ -2843,20 +2850,7 @@ nv50_display_create(struct drm_device *dev)
|
||||
dev->mode_config.normalize_zpos = true;
|
||||
|
||||
/* small shared memory area we use for notifiers and semaphores */
|
||||
ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
|
||||
NOUVEAU_GEM_DOMAIN_VRAM,
|
||||
0, 0x0000, NULL, NULL, &disp->sync);
|
||||
if (!ret) {
|
||||
ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
|
||||
if (!ret) {
|
||||
ret = nouveau_bo_map(disp->sync);
|
||||
if (ret)
|
||||
nouveau_bo_unpin(disp->sync);
|
||||
}
|
||||
if (ret)
|
||||
nouveau_bo_fini(disp->sync);
|
||||
}
|
||||
|
||||
ret = nouveau_bo_new_map(&drm->client, NOUVEAU_GEM_DOMAIN_VRAM, PAGE_SIZE, &disp->sync);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
|
||||
@@ -577,6 +577,7 @@ nv50_head_create(struct drm_device *dev, int index)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
head->func = disp->core->func->head;
|
||||
head->disp = disp;
|
||||
head->base.index = index;
|
||||
|
||||
if (disp->disp->object.oclass < GF110_DISP)
|
||||
|
||||
@@ -13,6 +13,8 @@
|
||||
|
||||
struct nv50_head {
|
||||
const struct nv50_head_func *func;
|
||||
struct nv50_disp *disp;
|
||||
|
||||
struct nouveau_crtc base;
|
||||
struct nv50_crc crc;
|
||||
struct nv50_lut olut;
|
||||
@@ -98,4 +100,7 @@ int headc37d_dither(struct nv50_head *, struct nv50_head_atom *);
|
||||
void headc37d_static_wndw_map(struct nv50_head *, struct nv50_head_atom *);
|
||||
|
||||
extern const struct nv50_head_func headc57d;
|
||||
bool headc57d_olut(struct nv50_head *, struct nv50_head_atom *, int size);
|
||||
|
||||
extern const struct nv50_head_func headca7d;
|
||||
#endif
|
||||
|
||||
@@ -182,7 +182,7 @@ headc57d_olut_load(struct drm_color_lut *in, int size, void __iomem *mem)
|
||||
writew(readw(mem - 4), mem + 4);
|
||||
}
|
||||
|
||||
static bool
|
||||
bool
|
||||
headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
|
||||
{
|
||||
if (size != 0 && size != 256 && size != 1024)
|
||||
|
||||
297
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
Normal file
297
drivers/gpu/drm/nouveau/dispnv50/headca7d.c
Normal file
@@ -0,0 +1,297 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#include "head.h"
|
||||
#include "atom.h"
|
||||
#include "core.h"
|
||||
|
||||
#include <nvif/pushc97b.h>
|
||||
|
||||
#include <nvhw/class/clca7d.h>
|
||||
|
||||
static int
|
||||
headca7d_display_id(struct nv50_head *head, u32 display_id)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_DISPLAY_ID(i, 0), display_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
u8 depth;
|
||||
int ret;
|
||||
|
||||
switch (asyh->or.depth) {
|
||||
case 6:
|
||||
depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444;
|
||||
break;
|
||||
case 5:
|
||||
depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444;
|
||||
break;
|
||||
case 2:
|
||||
depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444;
|
||||
break;
|
||||
case 0:
|
||||
depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444;
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, EXT_PACKET_WIN, NONE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_PROCAMP(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |
|
||||
NVDEF(NVCA7D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) |
|
||||
NVDEF(NVCA7D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_DITHER_CONTROL(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |
|
||||
NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |
|
||||
NVDEF(NVCA7D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) |
|
||||
NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |
|
||||
NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_curs_clr(struct nv50_head *head)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 4);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, DISABLE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const u32 curs_hi = upper_32_bits(asyh->curs.offset);
|
||||
const u32 curs_lo = lower_32_bits(asyh->curs.offset);
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 7);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(i, 0), curs_hi);
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(i, 0),
|
||||
NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ADDRESS_LO, curs_lo >> 4) |
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, TARGET, PHYSICAL_NVM) |
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, ENABLE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL_CURSOR(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0),
|
||||
|
||||
HEAD_SET_CONTROL_CURSOR_COMPOSITION(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, K1, 0xff) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT,
|
||||
K1) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT,
|
||||
NEG_K1_TIMES_SRC) |
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_olut_clr(struct nv50_head *head)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, DISABLE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const u32 olut_hi = upper_32_bits(asyh->olut.offset);
|
||||
const u32 olut_lo = lower_32_bits(asyh->olut.offset);
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 6);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_SURFACE_ADDRESS_HI_OLUT(i), olut_hi,
|
||||
|
||||
HEAD_SET_SURFACE_ADDRESS_LO_OLUT(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ADDRESS_LO, olut_lo >> 4) |
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, TARGET, PHYSICAL_NVM) |
|
||||
NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, ENABLE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_OLUT_CONTROL(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, INTERPOLATE, asyh->olut.output_mode) |
|
||||
NVDEF(NVCA7D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) |
|
||||
NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) |
|
||||
NVVAL(NVCA7D, HEAD_SET_OLUT_CONTROL, SIZE, asyh->olut.size),
|
||||
|
||||
HEAD_SET_OLUT_FP_NORM_SCALE(i), 0xffffffff);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
struct nv50_head_mode *m = &asyh->mode;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 11);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_RASTER_SIZE(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
|
||||
|
||||
HEAD_SET_RASTER_SYNC_END(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
|
||||
|
||||
HEAD_SET_RASTER_BLANK_END(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
|
||||
|
||||
HEAD_SET_RASTER_BLANK_START(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |
|
||||
NVVAL(NVCA7D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_CONTROL(i),
|
||||
NVDEF(NVCA7D, HEAD_SET_CONTROL, STRUCTURE, PROGRESSIVE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
headca7d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
|
||||
{
|
||||
struct nvif_push *push = &head->disp->core->chan.push;
|
||||
const int i = head->base.index;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 4);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
|
||||
NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
|
||||
|
||||
PUSH_MTHD(push, NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
|
||||
NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
|
||||
NVVAL(NVCA7D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH));
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct nv50_head_func
|
||||
headca7d = {
|
||||
.view = headca7d_view,
|
||||
.mode = headca7d_mode,
|
||||
.olut = headc57d_olut,
|
||||
.ilut_check = head907d_ilut_check,
|
||||
.olut_identity = true,
|
||||
.olut_size = 1024,
|
||||
.olut_set = headca7d_olut_set,
|
||||
.olut_clr = headca7d_olut_clr,
|
||||
.curs_layout = head917d_curs_layout,
|
||||
.curs_format = headc37d_curs_format,
|
||||
.curs_set = headca7d_curs_set,
|
||||
.curs_clr = headca7d_curs_clr,
|
||||
.dither = headca7d_dither,
|
||||
.procamp = headca7d_procamp,
|
||||
.or = headca7d_or,
|
||||
.static_wndw_map = headc37d_static_wndw_map,
|
||||
.display_id = headca7d_display_id,
|
||||
};
|
||||
@@ -31,6 +31,7 @@ nv50_wimm_init(struct nouveau_drm *drm, struct nv50_wndw *wndw)
|
||||
int version;
|
||||
int (*init)(struct nouveau_drm *, s32, struct nv50_wndw *);
|
||||
} wimms[] = {
|
||||
{ GB202_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
|
||||
{ GA102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
|
||||
{ TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
|
||||
{ GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
|
||||
|
||||
@@ -556,14 +556,24 @@ nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
|
||||
return ret;
|
||||
|
||||
if (wndw->ctxdma.parent) {
|
||||
ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
|
||||
if (IS_ERR(ctxdma)) {
|
||||
nouveau_bo_unpin(nvbo);
|
||||
return PTR_ERR(ctxdma);
|
||||
}
|
||||
if (wndw->wndw.base.user.oclass < GB202_DISP_WINDOW_CHANNEL_DMA) {
|
||||
ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
|
||||
if (IS_ERR(ctxdma)) {
|
||||
nouveau_bo_unpin(nvbo);
|
||||
return PTR_ERR(ctxdma);
|
||||
}
|
||||
|
||||
if (asyw->visible)
|
||||
asyw->image.handle[0] = ctxdma->object.handle;
|
||||
if (asyw->visible)
|
||||
asyw->image.handle[0] = ctxdma->object.handle;
|
||||
} else {
|
||||
/* No CTXDMAs on Blackwell. */
|
||||
if (asyw->visible) {
|
||||
/* "handle != NULL_HANDLE" is used to determine enable status
|
||||
* in a number of places, so fill in a fake object handle.
|
||||
*/
|
||||
asyw->image.handle[0] = NV50_DISP_HANDLE_WNDW_CTX(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = drm_gem_plane_helper_prepare_fb(plane, state);
|
||||
@@ -901,6 +911,7 @@ nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
|
||||
int (*new)(struct nouveau_drm *, enum drm_plane_type,
|
||||
int, s32, struct nv50_wndw **);
|
||||
} wndws[] = {
|
||||
{ GB202_DISP_WINDOW_CHANNEL_DMA, 0, wndwca7e_new },
|
||||
{ GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new },
|
||||
{ TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
|
||||
{ GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
|
||||
|
||||
@@ -134,6 +134,9 @@ int wndwc57e_csc_clr(struct nv50_wndw *);
|
||||
int wndwc67e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
|
||||
struct nv50_wndw **);
|
||||
|
||||
int wndwca7e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
|
||||
struct nv50_wndw **);
|
||||
|
||||
int nv50_wndw_new(struct nouveau_drm *, enum drm_plane_type, int index,
|
||||
struct nv50_wndw **);
|
||||
#endif
|
||||
|
||||
@@ -25,6 +25,7 @@
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <nouveau_bo.h>
|
||||
|
||||
#include <nvif/class.h>
|
||||
#include <nvif/if0014.h>
|
||||
#include <nvif/pushc37b.h>
|
||||
|
||||
|
||||
209
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
Normal file
209
drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c
Normal file
@@ -0,0 +1,209 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#include "wndw.h"
|
||||
#include "atom.h"
|
||||
|
||||
#include <nvif/pushc97b.h>
|
||||
|
||||
#include <nvhw/class/clca7e.h>
|
||||
|
||||
#include <nouveau_bo.h>
|
||||
|
||||
static int
|
||||
wndwca7e_image_clr(struct nv50_wndw *wndw)
|
||||
{
|
||||
struct nvif_push *push = &wndw->wndw.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 4);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
|
||||
NVVAL(NVCA7E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, 0) |
|
||||
NVDEF(NVCA7E, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, DISABLE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
wndwca7e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
|
||||
{
|
||||
const u32 iso0_hi = upper_32_bits(asyw->image.offset[0]);
|
||||
const u32 iso0_lo = lower_32_bits(asyw->image.offset[0]);
|
||||
struct nvif_push *push = &wndw->wndw.push;
|
||||
int ret, kind;
|
||||
|
||||
if (asyw->image.kind)
|
||||
kind = NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR;
|
||||
else
|
||||
kind = NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH;
|
||||
|
||||
ret = PUSH_WAIT(push, 17);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ISO(0), iso0_hi);
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ISO(0),
|
||||
NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ADDRESS_LO, iso0_lo >> 4) |
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, TARGET, PHYSICAL_NVM) |
|
||||
NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, KIND, kind) |
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, ENABLE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_PRESENT_CONTROL,
|
||||
NVVAL(NVCA7E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) |
|
||||
NVVAL(NVCA7E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
|
||||
NVDEF(NVCA7E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SIZE,
|
||||
NVVAL(NVCA7E, SET_SIZE, WIDTH, asyw->image.w) |
|
||||
NVVAL(NVCA7E, SET_SIZE, HEIGHT, asyw->image.h),
|
||||
|
||||
SET_STORAGE,
|
||||
NVVAL(NVCA7E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh),
|
||||
|
||||
SET_PARAMS,
|
||||
NVVAL(NVCA7E, SET_PARAMS, FORMAT, asyw->image.format) |
|
||||
NVDEF(NVCA7E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) |
|
||||
NVDEF(NVCA7E, SET_PARAMS, SWAP_UV, DISABLE) |
|
||||
NVDEF(NVCA7E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),
|
||||
|
||||
SET_PLANAR_STORAGE(0),
|
||||
NVVAL(NVCA7E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) |
|
||||
NVVAL(NVCA7E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_POINT_IN(0),
|
||||
NVVAL(NVCA7E, SET_POINT_IN, X, asyw->state.src_x >> 16) |
|
||||
NVVAL(NVCA7E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SIZE_IN,
|
||||
NVVAL(NVCA7E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) |
|
||||
NVVAL(NVCA7E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SIZE_OUT,
|
||||
NVVAL(NVCA7E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) |
|
||||
NVVAL(NVCA7E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
wndwca7e_ilut_clr(struct nv50_wndw *wndw)
|
||||
{
|
||||
struct nvif_push *push = &wndw->wndw.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT,
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, DISABLE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
wndwca7e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
|
||||
{
|
||||
const u32 ilut_hi = upper_32_bits(asyw->xlut.i.offset);
|
||||
const u32 ilut_lo = lower_32_bits(asyw->xlut.i.offset);
|
||||
struct nvif_push *push = &wndw->wndw.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 5);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_ILUT, ilut_hi,
|
||||
|
||||
SET_SURFACE_ADDRESS_LO_ILUT,
|
||||
NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ADDRESS_LO, ilut_lo >> 4) |
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, TARGET, PHYSICAL_NVM) |
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, ENABLE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_ILUT_CONTROL,
|
||||
NVVAL(NVCA7E, SET_ILUT_CONTROL, SIZE, asyw->xlut.i.size) |
|
||||
NVVAL(NVCA7E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) |
|
||||
NVVAL(NVCA7E, SET_ILUT_CONTROL, INTERPOLATE, asyw->xlut.i.output_mode));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
wndwca7e_ntfy_clr(struct nv50_wndw *wndw)
|
||||
{
|
||||
struct nvif_push *push = &wndw->wndw.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 2);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER,
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, DISABLE));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
wndwca7e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
|
||||
{
|
||||
struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
|
||||
const u64 ntfy_addr = disp->sync->offset + asyw->ntfy.offset;
|
||||
const u32 ntfy_hi = upper_32_bits(ntfy_addr);
|
||||
const u32 ntfy_lo = lower_32_bits(ntfy_addr);
|
||||
struct nvif_push *push = &wndw->wndw.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 5);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_SURFACE_ADDRESS_HI_NOTIFIER, ntfy_hi,
|
||||
|
||||
SET_SURFACE_ADDRESS_LO_NOTIFIER,
|
||||
NVVAL(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ADDRESS_LO, ntfy_lo >> 4) |
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, TARGET, PHYSICAL_NVM) |
|
||||
NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE));
|
||||
|
||||
PUSH_MTHD(push, NVCA7E, SET_NOTIFIER_CONTROL,
|
||||
NVVAL(NVCA7E, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct nv50_wndw_func
|
||||
wndwca7e = {
|
||||
.acquire = wndwc37e_acquire,
|
||||
.release = wndwc37e_release,
|
||||
.ntfy_set = wndwca7e_ntfy_set,
|
||||
.ntfy_clr = wndwca7e_ntfy_clr,
|
||||
.ntfy_reset = corec37d_ntfy_init,
|
||||
.ntfy_wait_begun = base507c_ntfy_wait_begun,
|
||||
.ilut = wndwc57e_ilut,
|
||||
.ilut_identity = true,
|
||||
.ilut_size = 1024,
|
||||
.xlut_set = wndwca7e_ilut_set,
|
||||
.xlut_clr = wndwca7e_ilut_clr,
|
||||
.csc = base907c_csc,
|
||||
.csc_set = wndwc57e_csc_set,
|
||||
.csc_clr = wndwc57e_csc_clr,
|
||||
.image_set = wndwca7e_image_set,
|
||||
.image_clr = wndwca7e_image_clr,
|
||||
.blend_set = wndwc37e_blend_set,
|
||||
.update = wndwc37e_update,
|
||||
};
|
||||
|
||||
int
|
||||
wndwca7e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
|
||||
s32 oclass, struct nv50_wndw **pwndw)
|
||||
{
|
||||
return wndwc37e_new_(&wndwca7e, drm, type, index, oclass, BIT(index >> 1), pwndw);
|
||||
}
|
||||
93
drivers/gpu/drm/nouveau/gv100_fence.c
Normal file
93
drivers/gpu/drm/nouveau/gv100_fence.c
Normal file
@@ -0,0 +1,93 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#include "nouveau_drv.h"
|
||||
#include "nouveau_dma.h"
|
||||
#include "nouveau_fence.h"
|
||||
|
||||
#include "nv50_display.h"
|
||||
|
||||
#include <nvif/push906f.h>
|
||||
|
||||
#include <nvhw/class/clc36f.h>
|
||||
|
||||
static int
|
||||
gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
|
||||
{
|
||||
struct nvif_push *push = &chan->chan.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 8);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
|
||||
SEM_ADDR_HI, upper_32_bits(virtual),
|
||||
SEM_PAYLOAD_LO, sequence);
|
||||
|
||||
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
|
||||
NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) |
|
||||
NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) |
|
||||
NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
|
||||
NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));
|
||||
|
||||
PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
|
||||
|
||||
PUSH_KICK(push);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gv100_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
|
||||
{
|
||||
struct nvif_push *push = &chan->chan.push;
|
||||
int ret;
|
||||
|
||||
ret = PUSH_WAIT(push, 6);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
|
||||
SEM_ADDR_HI, upper_32_bits(virtual),
|
||||
SEM_PAYLOAD_LO, sequence);
|
||||
|
||||
PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
|
||||
NVDEF(NVC36F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) |
|
||||
NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) |
|
||||
NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT));
|
||||
|
||||
PUSH_KICK(push);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gv100_fence_context_new(struct nouveau_channel *chan)
|
||||
{
|
||||
struct nv84_fence_chan *fctx;
|
||||
int ret;
|
||||
|
||||
ret = nv84_fence_context_new(chan);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
fctx = chan->fence;
|
||||
fctx->base.emit32 = gv100_fence_emit32;
|
||||
fctx->base.sync32 = gv100_fence_sync32;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
gv100_fence_create(struct nouveau_drm *drm)
|
||||
{
|
||||
struct nv84_fence_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nv84_fence_create(drm);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv = drm->fence;
|
||||
priv->base.context_new = gv100_fence_context_new;
|
||||
return 0;
|
||||
}
|
||||
52
drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h
Normal file
52
drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h
Normal file
@@ -0,0 +1,52 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef _clc36f_h_
|
||||
#define _clc36f_h_
|
||||
|
||||
#define NVC36F_NON_STALL_INTERRUPT (0x00000020)
|
||||
#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0
|
||||
#define NVC36F_SEM_ADDR_LO (0x0000005c)
|
||||
#define NVC36F_SEM_ADDR_LO_OFFSET 31:2
|
||||
#define NVC36F_SEM_ADDR_HI (0x00000060)
|
||||
#define NVC36F_SEM_ADDR_HI_OFFSET 7:0
|
||||
#define NVC36F_SEM_PAYLOAD_LO (0x00000064)
|
||||
#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0
|
||||
#define NVC36F_SEM_PAYLOAD_HI (0x00000068)
|
||||
#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0
|
||||
#define NVC36F_SEM_EXECUTE (0x0000006c)
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION 2:0
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005
|
||||
#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006
|
||||
#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
|
||||
#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000
|
||||
#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
|
||||
#define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20
|
||||
#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
|
||||
#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001
|
||||
#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
|
||||
#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
|
||||
#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001
|
||||
#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
|
||||
#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
|
||||
#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION 30:27
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000
|
||||
#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001
|
||||
|
||||
#endif
|
||||
22
drivers/gpu/drm/nouveau/include/nvhw/class/clc97b.h
Normal file
22
drivers/gpu/drm/nouveau/include/nvhw/class/clc97b.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef _clc97b_h_
|
||||
#define _clc97b_h_
|
||||
|
||||
// dma opcode instructions
|
||||
#define NVC97B_DMA
|
||||
#define NVC97B_DMA_OPCODE 31:29
|
||||
#define NVC97B_DMA_OPCODE_METHOD 0x00000000
|
||||
#define NVC97B_DMA_OPCODE_JUMP 0x00000001
|
||||
#define NVC97B_DMA_OPCODE_NONINC_METHOD 0x00000002
|
||||
#define NVC97B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003
|
||||
#define NVC97B_DMA_METHOD_COUNT 27:18
|
||||
#define NVC97B_DMA_METHOD_OFFSET 15:2
|
||||
#define NVC97B_DMA_DATA 31:0
|
||||
#define NVC97B_DMA_DATA_NOP 0x00000000
|
||||
#define NVC97B_DMA_JUMP_OFFSET 15:2
|
||||
#define NVC97B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0
|
||||
|
||||
#endif // _clc97b_h
|
||||
868
drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h
Normal file
868
drivers/gpu/drm/nouveau/include/nvhw/class/clca7d.h
Normal file
@@ -0,0 +1,868 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef _clca7d_h_
|
||||
#define _clca7d_h_
|
||||
|
||||
// class methods
|
||||
#define NVCA7D_UPDATE (0x00000200)
|
||||
#define NVCA7D_UPDATE_SPECIAL_HANDLING 21:20
|
||||
#define NVCA7D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000)
|
||||
#define NVCA7D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001)
|
||||
#define NVCA7D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002)
|
||||
#define NVCA7D_UPDATE_SPECIAL_HANDLING_REASON 19:12
|
||||
#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS 24:24
|
||||
#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000)
|
||||
#define NVCA7D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001)
|
||||
#define NVCA7D_UPDATE_RELEASE_ELV 0:0
|
||||
#define NVCA7D_UPDATE_RELEASE_ELV_FALSE (0x00000000)
|
||||
#define NVCA7D_UPDATE_RELEASE_ELV_TRUE (0x00000001)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN 8:4
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN__SIZE_1 16
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_0 (0x00000001)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_1 (0x00000002)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_2 (0x00000003)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_3 (0x00000004)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_4 (0x00000005)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_5 (0x00000006)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_6 (0x00000007)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_7 (0x00000008)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_8 (0x00000009)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_A (0x0000000B)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_B (0x0000000C)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_C (0x0000000D)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_D (0x0000000E)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_E (0x0000000F)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_LOCK_PIN_F (0x00000010)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
|
||||
#define NVCA7D_UPDATE_FLIP_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
|
||||
#define NVCA7D_UPDATE_FORCE_FULLSCREEN 28:28
|
||||
#define NVCA7D_UPDATE_FORCE_FULLSCREEN_FALSE (0x00000000)
|
||||
#define NVCA7D_UPDATE_FORCE_FULLSCREEN_TRUE (0x00000001)
|
||||
#define NVCA7D_SET_NOTIFIER_CONTROL (0x0000020C)
|
||||
#define NVCA7D_SET_NOTIFIER_CONTROL_MODE 0:0
|
||||
#define NVCA7D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
|
||||
#define NVCA7D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
|
||||
#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY 12:12
|
||||
#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS (0x00000218)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000260)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000264)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7D_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
|
||||
|
||||
#define NVCA7D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK 7:0
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040)
|
||||
#define NVCA7D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL 11:8
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_HDMI_FRL (0x0000000C)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
|
||||
#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16
|
||||
#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
|
||||
#define NVCA7D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
|
||||
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
|
||||
#define NVCA7D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
|
||||
|
||||
#define NVCA7D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER 3:0
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i))
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_HIDE 8:8
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_HIDE_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_HIDE_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS 9:9
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_DISABLE_PHYSICAL_FLIPS_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME 10:10
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_CONTROL_ALLOW_SUPERFRAME_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED 30:30
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT 26:25
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH_BLOCKLINEAR (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_PITCH (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_WINDOW_USAGE_BOUNDS_LAYOUT_BLOCKLINEAR (0x00000002)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL(a) (0x00001014 + (a)*0x00000080)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW 31:0
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_NONE (0x00000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW0 (0x00000001)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW1 (0x00000002)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW2 (0x00000004)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW3 (0x00000008)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW4 (0x00000010)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW5 (0x00000020)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW6 (0x00000040)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW7 (0x00000080)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW8 (0x00000100)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW9 (0x00000200)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW10 (0x00000400)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW11 (0x00000800)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW12 (0x00001000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW13 (0x00002000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW14 (0x00004000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW15 (0x00008000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW16 (0x00010000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW17 (0x00020000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW18 (0x00040000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW19 (0x00080000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW20 (0x00100000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW21 (0x00200000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW22 (0x00400000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW23 (0x00800000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW24 (0x01000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW25 (0x02000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW26 (0x04000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW27 (0x08000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW28 (0x10000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW29 (0x20000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW30 (0x40000000)
|
||||
#define NVCA7D_WINDOW_SET_PHYSICAL_WINDOW_WINDOW31 (0x80000000)
|
||||
|
||||
#define NVCA7D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V 4:4
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_CHROMA_DOWN_V_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_444 (0x00000009)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444NP (0x0000000A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL(a) (0x00002008 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STRUCTURE 1:0
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE 2:2
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_NORMAL (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO3D_STRUCTURE_FRAME_PACKED (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER 3:3
|
||||
#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_YUV420PACKER_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE 11:10
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_NO_LOCK (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_FRAME_LOCK (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_MODE_RASTER_LOCK (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN 8:4
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN__SIZE_1 16
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_0 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_1 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_2 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_3 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_4 (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_5 (0x00000006)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_6 (0x00000007)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_7 (0x00000008)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_8 (0x00000009)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_A (0x0000000B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_B (0x0000000C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_C (0x0000000D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_D (0x0000000E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_E (0x0000000F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_LOCK_PIN_F (0x00000010)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_LOCKOUT_WINDOW 15:12
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE 23:22
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_NO_LOCK (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_FRAME_LOCK (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_MODE_RASTER_LOCK (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN 20:16
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_NONE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN(i) (0x00000001 +(i))
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN__SIZE_1 16
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_0 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_1 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_2 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_3 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_4 (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_5 (0x00000006)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_6 (0x00000007)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_7 (0x00000008)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_8 (0x00000009)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_9 (0x0000000A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_A (0x0000000B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_B (0x0000000C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_C (0x0000000D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_D (0x0000000E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_E (0x0000000F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_LOCK_PIN_F (0x00000010)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_LOCK_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN 28:24
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_NONE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN(i) (0x00000001 +(i))
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN__SIZE_1 16
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_0 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_1 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_2 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_3 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_4 (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_5 (0x00000006)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_6 (0x00000007)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_7 (0x00000008)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_8 (0x00000009)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_9 (0x0000000A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_A (0x0000000B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_B (0x0000000C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_C (0x0000000D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_D (0x0000000E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_E (0x0000000F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_LOCK_PIN_F (0x00000010)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_0 (0x00000014)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_1 (0x00000015)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_2 (0x00000016)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_FLIP_LOCK_3 (0x00000017)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK(i) (0x00000018 +(i))
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK__SIZE_1 8
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_0 (0x00000018)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_1 (0x00000019)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_2 (0x0000001A)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_3 (0x0000001B)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_4 (0x0000001C)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_5 (0x0000001D)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_6 (0x0000001E)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_STEREO_PIN_INTERNAL_SCAN_LOCK_7 (0x0000001F)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE 30:30
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SINK_STEREO_LOCK_MODE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE 31:31
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_SOURCE_STEREO_LOCK_MODE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS 5:4
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE 10:8
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_MODE_ROUND (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_DITHER_CONTROL_PHASE 13:12
|
||||
#define NVCA7D_HEAD_SET_DISPLAY_ID(a,b) (0x00002020 + (a)*0x00000800 + (b)*0x00000004)
|
||||
#define NVCA7D_HEAD_SET_DISPLAY_ID_CODE 31:0
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED 5:5
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_FALSE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_LTM_ALLOWED_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED 16:16
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_FALSE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_OVERFETCH_ENABLED_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_HEAD_USAGE_BOUNDS_ELV_START 31:17
|
||||
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0
|
||||
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16
|
||||
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0
|
||||
#define NVCA7D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK(a) (0x00002060 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE 7:0
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_NONE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE0 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE1 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE2 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE3 (0x00000008)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE4 (0x00000010)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE5 (0x00000020)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE6 (0x00000040)
|
||||
#define NVCA7D_HEAD_SET_TILE_MASK_TILE_TILE7 (0x00000080)
|
||||
#define NVCA7D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_RASTER_SIZE_WIDTH 15:0
|
||||
#define NVCA7D_HEAD_SET_RASTER_SIZE_HEIGHT 31:16
|
||||
#define NVCA7D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_RASTER_SYNC_END_X 14:0
|
||||
#define NVCA7D_HEAD_SET_RASTER_SYNC_END_Y 30:16
|
||||
#define NVCA7D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_RASTER_BLANK_END_X 14:0
|
||||
#define NVCA7D_HEAD_SET_RASTER_BLANK_END_Y 30:16
|
||||
#define NVCA7D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_RASTER_BLANK_START_X 14:0
|
||||
#define NVCA7D_HEAD_SET_RASTER_BLANK_START_Y 30:16
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS 20:20
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_BYPASS_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC(a) (0x00002150 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CRC_ADDRESS_HI 31:0
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC(a) (0x00002154 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ADDRESS_LO 31:4
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET 3:2
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_IOVA (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE 0:0
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CRC_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT(a) (0x00002158 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_OLUT_ADDRESS_HI 31:0
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT(a) (0x0000215C + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ADDRESS_LO 31:4
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET 3:2
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_IOVA (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE 0:0
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_OLUT_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR(a,b) (0x00002170 + (a)*0x00000800 + (b)*0x00000004)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_HI_CURSOR_ADDRESS_HI 31:0
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR(a,b) (0x00002178 + (a)*0x00000800 + (b)*0x00000004)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ADDRESS_LO 31:4
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET 3:2
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_IOVA (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND 1:1
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_PITCH (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_KIND_BLOCKLINEAR (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE 0:0
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_SURFACE_ADDRESS_LO_CURSOR_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i))
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i))
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057)
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9
|
||||
#define NVCA7D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE 3:2
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SIZE 18:8
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND 4:4
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_DISABLE (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_DIRECT_ROUND_ENABLE (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_LEVEL 25:20
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS 5:5
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_3BITS (0x00000000)
|
||||
#define NVCA7D_HEAD_SET_OLUT_CONTROL_SEGMENT_SIZE_BITS_SIZE_4BITS (0x00000001)
|
||||
#define NVCA7D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000800)
|
||||
#define NVCA7D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0
|
||||
|
||||
#define NVCA7D_TILE_SET_TILE_SIZE(a) (0x00006000 + (a)*0x00000200)
|
||||
#define NVCA7D_TILE_SET_TILE_SIZE_START 14:0
|
||||
#define NVCA7D_TILE_SET_TILE_SIZE_WIDTH 30:16
|
||||
|
||||
#endif // _clca7d_h
|
||||
137
drivers/gpu/drm/nouveau/include/nvhw/class/clca7e.h
Normal file
137
drivers/gpu/drm/nouveau/include/nvhw/class/clca7e.h
Normal file
@@ -0,0 +1,137 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef _clca7e_h_
|
||||
#define _clca7e_h_
|
||||
|
||||
// class methods
|
||||
#define NVCA7E_SET_NOTIFIER_CONTROL (0x00000220)
|
||||
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE 0:0
|
||||
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000)
|
||||
#define NVCA7E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001)
|
||||
#define NVCA7E_SET_SIZE (0x00000224)
|
||||
#define NVCA7E_SET_SIZE_WIDTH 15:0
|
||||
#define NVCA7E_SET_SIZE_HEIGHT 31:16
|
||||
#define NVCA7E_SET_STORAGE (0x00000228)
|
||||
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT 3:0
|
||||
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000)
|
||||
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001)
|
||||
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002)
|
||||
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003)
|
||||
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004)
|
||||
#define NVCA7E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005)
|
||||
#define NVCA7E_SET_PARAMS (0x0000022C)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT 7:0
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_I8 (0x0000001E)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076)
|
||||
#define NVCA7E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078)
|
||||
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18
|
||||
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001)
|
||||
#define NVCA7E_SET_PARAMS_SWAP_UV 19:19
|
||||
#define NVCA7E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001)
|
||||
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE 22:22
|
||||
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000)
|
||||
#define NVCA7E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001)
|
||||
#define NVCA7E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004)
|
||||
#define NVCA7E_SET_PLANAR_STORAGE_PITCH 12:0
|
||||
#define NVCA7E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004)
|
||||
#define NVCA7E_SET_POINT_IN_X 15:0
|
||||
#define NVCA7E_SET_POINT_IN_Y 31:16
|
||||
#define NVCA7E_SET_SIZE_IN (0x00000298)
|
||||
#define NVCA7E_SET_SIZE_IN_WIDTH 15:0
|
||||
#define NVCA7E_SET_SIZE_IN_HEIGHT 31:16
|
||||
#define NVCA7E_SET_SIZE_OUT (0x000002A4)
|
||||
#define NVCA7E_SET_SIZE_OUT_WIDTH 15:0
|
||||
#define NVCA7E_SET_SIZE_OUT_HEIGHT 31:16
|
||||
#define NVCA7E_SET_PRESENT_CONTROL (0x00000308)
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000)
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001)
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001)
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE 13:12
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_MONO (0x00000000)
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_PAIR_FLIP (0x00000001)
|
||||
#define NVCA7E_SET_PRESENT_CONTROL_STEREO_MODE_AT_ANY_FRAME (0x00000002)
|
||||
#define NVCA7E_SET_ILUT_CONTROL (0x00000440)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE 0:0
|
||||
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_MIRROR 1:1
|
||||
#define NVCA7E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_MODE 3:2
|
||||
#define NVCA7E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002)
|
||||
#define NVCA7E_SET_ILUT_CONTROL_SIZE 18:8
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER (0x00000650)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_HI_NOTIFIER_ADDRESS_HI 31:0
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER (0x00000654)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ADDRESS_LO 31:4
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET 3:2
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_IOVA (0x00000000)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE 0:0
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_NOTIFIER_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO(b) (0x00000658 + (b)*0x00000004)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ISO_ADDRESS_HI 31:0
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO(b) (0x00000670 + (b)*0x00000004)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ADDRESS_LO 31:4
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET 3:2
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_IOVA (0x00000000)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND 1:1
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_PITCH (0x00000000)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_KIND_BLOCKLINEAR (0x00000001)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE 0:0
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ISO_ENABLE_ENABLE (0x00000001)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT (0x00000688)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_HI_ILUT_ADDRESS_HI 31:0
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT (0x0000068C)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ADDRESS_LO 31:4
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET 3:2
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_IOVA (0x00000000)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_NVM (0x00000001)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI (0x00000002)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_TARGET_PHYSICAL_PCI_COHERENT (0x00000003)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE 0:0
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_DISABLE (0x00000000)
|
||||
#define NVCA7E_SET_SURFACE_ADDRESS_LO_ILUT_ENABLE_ENABLE (0x00000001)
|
||||
|
||||
#endif // _clca7e_h
|
||||
@@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gb100_dev_hshub_base_h__
|
||||
#define __gb100_dev_hshub_base_h__
|
||||
|
||||
#define NV_PFB_HSHUB0 0x00870fff:0x00870000
|
||||
|
||||
#define NV_PFB_HSHUB 0x00000FFF:0x00000000 /* RW--D */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00000E50 /* RW-4R */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00000E54 /* RW-4R */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO 0x000006C0 /* RW-4R */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI 0x000006C4 /* RW-4R */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
|
||||
|
||||
#endif // __gb100_dev_hshub_base_h__
|
||||
18
drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h
Normal file
18
drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gb10b_dev_fb_h__
|
||||
#define __gb10b_dev_fb_h__
|
||||
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO 0x008a1d58 /* RW-4R */
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xffffff00 /* RW--V */
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI 0x008a1d5c /* RW-4R */
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000fffff /* RW--V */
|
||||
|
||||
#endif // __gb10b_dev_fb_h__
|
||||
|
||||
12
drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h
Normal file
12
drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h
Normal file
@@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gb202_dev_ce_h__
|
||||
#define __gb202_dev_ce_h__
|
||||
|
||||
#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */
|
||||
#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */
|
||||
#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
|
||||
|
||||
#endif // __gb202_dev_ce_h__
|
||||
17
drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h
Normal file
17
drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gb202_dev_therm_h__
|
||||
#define __gb202_dev_therm_h__
|
||||
|
||||
#define NV_THERM_I2CS_SCRATCH 0x00ad00bc /* RW-4R */
|
||||
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
|
||||
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
|
||||
|
||||
#endif // __gb202_dev_therm_h__
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_dev_falcon_v4_h__
|
||||
#define __gh100_dev_falcon_v4_h__
|
||||
|
||||
#define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */
|
||||
#define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
|
||||
#define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */
|
||||
#define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
|
||||
#define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
|
||||
|
||||
#define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */
|
||||
#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */
|
||||
#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */
|
||||
#define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */
|
||||
|
||||
#endif // __gh100_dev_falcon_v4_h__
|
||||
15
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_fb.h
Normal file
15
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_fb.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_dev_fb_h_
|
||||
#define __gh100_dev_fb_h_
|
||||
|
||||
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
|
||||
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00100A34 /* RW-4R */
|
||||
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */
|
||||
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
|
||||
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
|
||||
|
||||
#endif // __gh100_dev_fb_h_
|
||||
28
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_fsp_pri.h
Normal file
28
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_fsp_pri.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_dev_fsp_pri_h__
|
||||
#define __gh100_dev_fsp_pri_h__
|
||||
|
||||
#define NV_PFSP 0x8F3FFF:0x8F0000 /* RW--D */
|
||||
|
||||
#define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */
|
||||
#define NV_PFSP_MSGQ_HEAD__SIZE_1 8 /* */
|
||||
#define NV_PFSP_MSGQ_HEAD_VAL 31:0 /* RWIUF */
|
||||
#define NV_PFSP_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */
|
||||
#define NV_PFSP_MSGQ_TAIL__SIZE_1 8 /* */
|
||||
#define NV_PFSP_MSGQ_TAIL_VAL 31:0 /* RWIUF */
|
||||
#define NV_PFSP_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */
|
||||
|
||||
#define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */
|
||||
#define NV_PFSP_QUEUE_HEAD__SIZE_1 8 /* */
|
||||
#define NV_PFSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
|
||||
#define NV_PFSP_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */
|
||||
#define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */
|
||||
#define NV_PFSP_QUEUE_TAIL__SIZE_1 8 /* */
|
||||
#define NV_PFSP_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */
|
||||
#define NV_PFSP_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */
|
||||
|
||||
#endif // __gh100_dev_fsp_pri_h__
|
||||
173
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_mmu.h
Normal file
173
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_mmu.h
Normal file
@@ -0,0 +1,173 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_dev_mmu_h__
|
||||
#define __gh100_dev_mmu_h__
|
||||
|
||||
#define NV_MMU_PTE /* ----G */
|
||||
#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
|
||||
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
|
||||
#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
|
||||
#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
|
||||
#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
|
||||
#define NV_MMU_PTE_KIND (1*32+7):(1*32+4) /* RWXVF */
|
||||
#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */
|
||||
#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */
|
||||
#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */
|
||||
#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */
|
||||
#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */
|
||||
#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */
|
||||
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */
|
||||
|
||||
#define NV_MMU_VER3_PDE /* ----G */
|
||||
#define NV_MMU_VER3_PDE_IS_PTE 0:0 /* RWXVF */
|
||||
#define NV_MMU_VER3_PDE_IS_PTE_TRUE 0x1 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_IS_PTE_FALSE 0x0 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_VALID 0:0 /* RWXVF */
|
||||
#define NV_MMU_VER3_PDE_VALID_TRUE 0x1 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_VALID_FALSE 0x0 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_APERTURE 2:1 /* RWXVF */
|
||||
#define NV_MMU_VER3_PDE_APERTURE_INVALID 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF 5:3 /* RWXVF */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PDE_ADDRESS 51:12 /* RWXVF */
|
||||
#define NV_MMU_VER3_PDE_ADDRESS_SHIFT 0x0000000c /* */
|
||||
#define NV_MMU_VER3_PDE__SIZE 8
|
||||
|
||||
#define NV_MMU_VER3_DUAL_PDE /* ----G */
|
||||
#define NV_MMU_VER3_DUAL_PDE_IS_PTE 0:0 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_VALID 0:0 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG 5:3 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG 51:8 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL 69:67 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL 115:76 /* RWXVF */
|
||||
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */
|
||||
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */
|
||||
#define NV_MMU_VER3_DUAL_PDE__SIZE 16
|
||||
|
||||
#define NV_MMU_VER3_PTE /* ----G */
|
||||
#define NV_MMU_VER3_PTE_VALID 0:0 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_VALID_TRUE 0x1 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_VALID_FALSE 0x0 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_APERTURE 2:1 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF 7:3 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_PCF_INVALID 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_SPARSE 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE 0x00000004 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE 0x00000005 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE 0x00000006 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE 0x00000007 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE 0x00000008 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE 0x00000009 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE 0x0000000A /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE 0x0000000B /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE 0x0000000C /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000D /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE 0x0000000E /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000F /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD 0x00000010 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD 0x00000011 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD 0x00000012 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD 0x00000013 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD 0x00000014 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD 0x00000015 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD 0x00000016 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD 0x00000017 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD 0x00000018 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD 0x00000019 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD 0x0000001A /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD 0x0000001B /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD 0x0000001C /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001D /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD 0x0000001E /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001F /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_2 0x00000002 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_3 0x00000003 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_4 0x00000004 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_5 0x00000005 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_6 0x00000006 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_PEER_ID_7 0x00000007 /* RW--V */
|
||||
#define NV_MMU_VER3_PTE_ADDRESS_SHIFT 0x0000000c /* */
|
||||
#define NV_MMU_VER3_PTE__SIZE 8
|
||||
|
||||
#endif // __gh100_dev_mmu_h__
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_dev_riscv_pri_h__
|
||||
#define __gh100_dev_riscv_pri_h__
|
||||
|
||||
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RW-4R */
|
||||
#define NV_PRISCV_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
|
||||
#define NV_PRISCV_RISCV_CPUCTL_HALTED_INIT 0x00000001 /* R-I-V */
|
||||
#define NV_PRISCV_RISCV_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
|
||||
#define NV_PRISCV_RISCV_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
|
||||
|
||||
#endif // __gh100_dev_riscv_pri_h__
|
||||
17
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_therm.h
Normal file
17
drivers/gpu/drm/nouveau/include/nvhw/ref/gh100/dev_therm.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_dev_therm_h__
|
||||
#define __gh100_dev_therm_h__
|
||||
|
||||
#define NV_THERM_I2CS_SCRATCH 0x000200bc /* RW-4R */
|
||||
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
|
||||
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
|
||||
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
|
||||
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
|
||||
|
||||
#endif // __gh100_dev_therm_h__
|
||||
@@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_dev_xtl_ep_pri_h__
|
||||
#define __gh100_dev_xtl_ep_pri_h__
|
||||
|
||||
#define NV_EP_PCFGM 0x92FFF:0x92000 /* RW--D */
|
||||
|
||||
#endif // __gh100_dev_xtl_ep_pri_h__
|
||||
@@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __gh100_pri_nv_xal_ep_h__
|
||||
#define __gh100_pri_nv_xal_ep_h__
|
||||
|
||||
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x000010
|
||||
#define NV_XAL_EP_BAR0_WINDOW_BASE 21:0
|
||||
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40
|
||||
|
||||
#endif // __gh100_pri_nv_xal_ep_h__
|
||||
|
||||
76
drivers/gpu/drm/nouveau/include/nvif/chan.h
Normal file
76
drivers/gpu/drm/nouveau/include/nvif/chan.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __NVIF_CHAN_H__
|
||||
#define __NVIF_CHAN_H__
|
||||
#include "push.h"
|
||||
|
||||
struct nvif_chan {
|
||||
const struct nvif_chan_func {
|
||||
struct {
|
||||
u32 (*read_get)(struct nvif_chan *);
|
||||
} push;
|
||||
|
||||
struct {
|
||||
u32 (*read_get)(struct nvif_chan *);
|
||||
void (*push)(struct nvif_chan *, bool main, u64 addr, u32 size,
|
||||
bool no_prefetch);
|
||||
void (*kick)(struct nvif_chan *);
|
||||
int (*post)(struct nvif_chan *, u32 gpptr, u32 pbptr);
|
||||
u32 post_size;
|
||||
} gpfifo;
|
||||
|
||||
struct {
|
||||
int (*release)(struct nvif_chan *, u64 addr, u32 data);
|
||||
} sem;
|
||||
} *func;
|
||||
|
||||
struct {
|
||||
struct nvif_map map;
|
||||
} userd;
|
||||
|
||||
struct {
|
||||
struct nvif_map map;
|
||||
u32 cur;
|
||||
u32 max;
|
||||
int free;
|
||||
} gpfifo;
|
||||
|
||||
struct {
|
||||
struct nvif_map map;
|
||||
u64 addr;
|
||||
} sema;
|
||||
|
||||
struct nvif_push push;
|
||||
|
||||
struct nvif_user *usermode;
|
||||
u32 doorbell_token;
|
||||
};
|
||||
|
||||
int nvif_chan_dma_wait(struct nvif_chan *, u32 push_nr);
|
||||
|
||||
void nvif_chan_gpfifo_ctor(const struct nvif_chan_func *, void *userd, void *gpfifo, u32 gpfifo_size,
|
||||
void *push, u64 push_addr, u32 push_size, struct nvif_chan *);
|
||||
int nvif_chan_gpfifo_wait(struct nvif_chan *, u32 gpfifo_nr, u32 push_nr);
|
||||
void nvif_chan_gpfifo_push(struct nvif_chan *, u64 addr, u32 size, bool no_prefetch);
|
||||
int nvif_chan_gpfifo_post(struct nvif_chan *);
|
||||
|
||||
void nvif_chan506f_gpfifo_push(struct nvif_chan *, bool main, u64 addr, u32 size, bool no_prefetch);
|
||||
void nvif_chan506f_gpfifo_kick(struct nvif_chan *);
|
||||
|
||||
int nvif_chan906f_ctor_(const struct nvif_chan_func *, void *userd, void *gpfifo, u32 gpfifo_size,
|
||||
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
|
||||
struct nvif_chan *);
|
||||
u32 nvif_chan906f_read_get(struct nvif_chan *);
|
||||
u32 nvif_chan906f_gpfifo_read_get(struct nvif_chan *);
|
||||
int nvif_chan906f_gpfifo_post(struct nvif_chan *, u32 gpptr, u32 pbptr);
|
||||
|
||||
int nvif_chan506f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size,
|
||||
void *push, u64 push_addr, u32 push_size);
|
||||
int nvif_chan906f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size,
|
||||
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr);
|
||||
int nvif_chanc36f_ctor(struct nvif_chan *, void *userd, void *gpfifo, u32 gpfifo_size,
|
||||
void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
|
||||
struct nvif_user *usermode, u32 doorbell_token);
|
||||
#endif
|
||||
@@ -29,6 +29,8 @@ struct nv_device_info_v0 {
|
||||
#define NV_DEVICE_INFO_V0_TURING 0x0c
|
||||
#define NV_DEVICE_INFO_V0_AMPERE 0x0d
|
||||
#define NV_DEVICE_INFO_V0_ADA 0x0e
|
||||
#define NV_DEVICE_INFO_V0_HOPPER 0x0f
|
||||
#define NV_DEVICE_INFO_V0_BLACKWELL 0x10
|
||||
__u8 family;
|
||||
__u8 pad06[2];
|
||||
__u64 ram_size;
|
||||
|
||||
@@ -57,12 +57,15 @@
|
||||
|
||||
#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
|
||||
#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
|
||||
#define BLACKWELL_INLINE_TO_MEMORY_A 0x0000cd40
|
||||
|
||||
#define NV04_DISP /* cl0046.h */ 0x00000046
|
||||
|
||||
#define VOLTA_USERMODE_A 0x0000c361
|
||||
#define TURING_USERMODE_A 0x0000c461
|
||||
#define AMPERE_USERMODE_A 0x0000c561
|
||||
#define HOPPER_USERMODE_A 0x0000c661
|
||||
#define BLACKWELL_USERMODE_A 0x0000c761
|
||||
|
||||
#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
|
||||
#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
|
||||
@@ -85,6 +88,9 @@
|
||||
#define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f
|
||||
#define AMPERE_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c56f
|
||||
#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
|
||||
#define HOPPER_CHANNEL_GPFIFO_A 0x0000c86f
|
||||
#define BLACKWELL_CHANNEL_GPFIFO_A 0x0000c96f
|
||||
#define BLACKWELL_CHANNEL_GPFIFO_B 0x0000ca6f
|
||||
|
||||
#define NV50_DISP /* if0010.h */ 0x00005070
|
||||
#define G82_DISP /* if0010.h */ 0x00008270
|
||||
@@ -102,8 +108,10 @@
|
||||
#define TU102_DISP /* if0010.h */ 0x0000c570
|
||||
#define GA102_DISP /* if0010.h */ 0x0000c670
|
||||
#define AD102_DISP /* if0010.h */ 0x0000c770
|
||||
#define GB202_DISP 0x0000ca70
|
||||
|
||||
#define GV100_DISP_CAPS 0x0000c373
|
||||
#define GB202_DISP_CAPS 0x0000ca73
|
||||
|
||||
#define NV31_MPEG 0x00003174
|
||||
#define G82_MPEG 0x00008274
|
||||
@@ -118,6 +126,7 @@
|
||||
#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a
|
||||
#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a
|
||||
#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a
|
||||
#define GB202_DISP_CURSOR 0x0000ca7a
|
||||
|
||||
#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b
|
||||
#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b
|
||||
@@ -128,6 +137,7 @@
|
||||
#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b
|
||||
#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b
|
||||
#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b
|
||||
#define GB202_DISP_WINDOW_IMM_CHANNEL_DMA 0x0000ca7b
|
||||
|
||||
#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c
|
||||
#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c
|
||||
@@ -153,6 +163,7 @@
|
||||
#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
|
||||
#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
|
||||
#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
|
||||
#define GB202_DISP_CORE_CHANNEL_DMA 0x0000ca7d
|
||||
|
||||
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
|
||||
#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
|
||||
@@ -164,6 +175,7 @@
|
||||
#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e
|
||||
#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e
|
||||
#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e
|
||||
#define GB202_DISP_WINDOW_CHANNEL_DMA 0x0000ca7e
|
||||
|
||||
#define NV50_TESLA 0x00005097
|
||||
#define G82_TESLA 0x00008297
|
||||
@@ -189,16 +201,25 @@
|
||||
|
||||
#define TURING_A /* cl9097.h */ 0x0000c597
|
||||
|
||||
#define AMPERE_A 0x0000c697
|
||||
#define AMPERE_B /* cl9097.h */ 0x0000c797
|
||||
|
||||
#define ADA_A /* cl9097.h */ 0x0000c997
|
||||
|
||||
#define HOPPER_A 0x0000cb97
|
||||
|
||||
#define BLACKWELL_A 0x0000cd97
|
||||
#define BLACKWELL_B 0x0000ce97
|
||||
|
||||
#define NV74_BSP 0x000074b0
|
||||
|
||||
#define NVB8B0_VIDEO_DECODER 0x0000b8b0
|
||||
#define NVC4B0_VIDEO_DECODER 0x0000c4b0
|
||||
#define NVC6B0_VIDEO_DECODER 0x0000c6b0
|
||||
#define NVC7B0_VIDEO_DECODER 0x0000c7b0
|
||||
#define NVC9B0_VIDEO_DECODER 0x0000c9b0
|
||||
#define NVCDB0_VIDEO_DECODER 0x0000cdb0
|
||||
#define NVCFB0_VIDEO_DECODER 0x0000cfb0
|
||||
|
||||
#define GT212_MSVLD 0x000085b1
|
||||
#define IGT21A_MSVLD 0x000086b1
|
||||
@@ -227,10 +248,14 @@
|
||||
#define TURING_DMA_COPY_A 0x0000c5b5
|
||||
#define AMPERE_DMA_COPY_A 0x0000c6b5
|
||||
#define AMPERE_DMA_COPY_B 0x0000c7b5
|
||||
#define HOPPER_DMA_COPY_A 0x0000c8b5
|
||||
#define BLACKWELL_DMA_COPY_A 0x0000c9b5
|
||||
#define BLACKWELL_DMA_COPY_B 0x0000cab5
|
||||
|
||||
#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
|
||||
#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
|
||||
#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
|
||||
#define NVCFB7_VIDEO_ENCODER 0x0000cfb7
|
||||
|
||||
#define FERMI_DECOMPRESS 0x000090b8
|
||||
|
||||
@@ -246,15 +271,25 @@
|
||||
#define PASCAL_COMPUTE_B 0x0000c1c0
|
||||
#define VOLTA_COMPUTE_A 0x0000c3c0
|
||||
#define TURING_COMPUTE_A 0x0000c5c0
|
||||
#define AMPERE_COMPUTE_A 0x0000c6c0
|
||||
#define AMPERE_COMPUTE_B 0x0000c7c0
|
||||
#define ADA_COMPUTE_A 0x0000c9c0
|
||||
#define HOPPER_COMPUTE_A 0x0000cbc0
|
||||
#define BLACKWELL_COMPUTE_A 0x0000cdc0
|
||||
#define BLACKWELL_COMPUTE_B 0x0000cec0
|
||||
|
||||
#define NV74_CIPHER 0x000074c1
|
||||
|
||||
#define NVB8D1_VIDEO_NVJPG 0x0000b8d1
|
||||
#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
|
||||
#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
|
||||
#define NVCDD1_VIDEO_NVJPG 0x0000cdd1
|
||||
#define NVCFD1_VIDEO_NVJPG 0x0000cfd1
|
||||
|
||||
#define NVB8FA_VIDEO_OFA 0x0000b8fa
|
||||
#define NVC6FA_VIDEO_OFA 0x0000c6fa
|
||||
#define NVC7FA_VIDEO_OFA 0x0000c7fa
|
||||
#define NVC9FA_VIDEO_OFA 0x0000c9fa
|
||||
#define NVCDFA_VIDEO_OFA 0x0000cdfa
|
||||
#define NVCFFA_VIDEO_OFA 0x0000cffa
|
||||
#endif
|
||||
|
||||
@@ -16,7 +16,7 @@ struct nvif_object {
|
||||
u32 handle;
|
||||
s32 oclass;
|
||||
void *priv; /*XXX: hack */
|
||||
struct {
|
||||
struct nvif_map {
|
||||
void __iomem *ptr;
|
||||
u64 size;
|
||||
} map;
|
||||
|
||||
@@ -31,6 +31,12 @@ struct nvif_push {
|
||||
void (*kick)(struct nvif_push *push);
|
||||
|
||||
struct nvif_mem mem;
|
||||
u64 addr;
|
||||
|
||||
struct {
|
||||
u32 get;
|
||||
u32 max;
|
||||
} hw;
|
||||
|
||||
u32 *bgn;
|
||||
u32 *cur;
|
||||
@@ -41,7 +47,7 @@ struct nvif_push {
|
||||
static inline __must_check int
|
||||
PUSH_WAIT(struct nvif_push *push, u32 size)
|
||||
{
|
||||
if (push->cur + size >= push->end) {
|
||||
if (push->cur + size > push->end) {
|
||||
int ret = push->wait(push, size);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -55,7 +61,11 @@ PUSH_WAIT(struct nvif_push *push, u32 size)
|
||||
static inline int
|
||||
PUSH_KICK(struct nvif_push *push)
|
||||
{
|
||||
push->kick(push);
|
||||
if (push->cur != push->bgn) {
|
||||
push->kick(push);
|
||||
push->bgn = push->cur;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#ifndef PUSH906F_SUBC
|
||||
// Host methods
|
||||
#define PUSH906F_SUBC_NV906F 0
|
||||
#define PUSH906F_SUBC_NVC36F 0
|
||||
|
||||
// Twod
|
||||
#define PUSH906F_SUBC_NV902D 3
|
||||
|
||||
18
drivers/gpu/drm/nouveau/include/nvif/pushc97b.h
Normal file
18
drivers/gpu/drm/nouveau/include/nvif/pushc97b.h
Normal file
@@ -0,0 +1,18 @@
|
||||
#ifndef __NVIF_PUSHC97B_H__
|
||||
#define __NVIF_PUSHC97B_H__
|
||||
#include <nvif/push.h>
|
||||
|
||||
#include <nvhw/class/clc97b.h>
|
||||
|
||||
#define PUSH_HDR(p,m,c) do { \
|
||||
PUSH_ASSERT(!((m) & ~DRF_SMASK(NVC97B_DMA_METHOD_OFFSET)), "mthd"); \
|
||||
PUSH_ASSERT(!((c) & ~DRF_MASK(NVC97B_DMA_METHOD_COUNT)), "size"); \
|
||||
PUSH_DATA__((p), NVDEF(NVC97B, DMA, OPCODE, METHOD) | \
|
||||
NVVAL(NVC97B, DMA, METHOD_COUNT, (c)) | \
|
||||
NVVAL(NVC97B, DMA, METHOD_OFFSET, (m) >> 2), \
|
||||
" mthd 0x%04x size %d - %s", (u32)(m), (u32)(c), __func__); \
|
||||
} while(0)
|
||||
|
||||
#define PUSH_MTHD_HDR(p,s,m,c) PUSH_HDR(p,m,c)
|
||||
#define PUSH_MTHD_INC 4:4
|
||||
#endif
|
||||
@@ -46,7 +46,10 @@ struct nvkm_device {
|
||||
GV100 = 0x140,
|
||||
TU100 = 0x160,
|
||||
GA100 = 0x170,
|
||||
GH100 = 0x180,
|
||||
AD100 = 0x190,
|
||||
GB10x = 0x1a0,
|
||||
GB20x = 0x1b0,
|
||||
} card_type;
|
||||
u32 chipset;
|
||||
u8 chiprev;
|
||||
@@ -77,6 +80,13 @@ struct nvkm_device {
|
||||
struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int type, int inst);
|
||||
struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int type, int inst);
|
||||
|
||||
enum nvkm_bar_id {
|
||||
NVKM_BAR_INVALID = 0,
|
||||
NVKM_BAR0_PRI,
|
||||
NVKM_BAR1_FB,
|
||||
NVKM_BAR2_INST,
|
||||
};
|
||||
|
||||
struct nvkm_device_func {
|
||||
struct nvkm_device_pci *(*pci)(struct nvkm_device *);
|
||||
struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
|
||||
@@ -85,8 +95,8 @@ struct nvkm_device_func {
|
||||
int (*init)(struct nvkm_device *);
|
||||
void (*fini)(struct nvkm_device *, bool suspend);
|
||||
int (*irq)(struct nvkm_device *);
|
||||
resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar);
|
||||
resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar);
|
||||
resource_size_t (*resource_addr)(struct nvkm_device *, enum nvkm_bar_id);
|
||||
resource_size_t (*resource_size)(struct nvkm_device *, enum nvkm_bar_id);
|
||||
bool cpu_coherent;
|
||||
};
|
||||
|
||||
@@ -124,6 +134,9 @@ struct nvkm_device *nvkm_device_find(u64 name);
|
||||
_temp; \
|
||||
})
|
||||
|
||||
#define NVKM_RD32_(p,o,dr) nvkm_rd32((p), (o) + (dr))
|
||||
#define NVKM_RD32(p,A...) DRF_RV(NVKM_RD32_, (p), 0, ##A)
|
||||
|
||||
void nvkm_device_del(struct nvkm_device **);
|
||||
|
||||
struct nvkm_device_oclass {
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FSP , struct nvkm_fsp , fsp)
|
||||
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_GSP , struct nvkm_gsp , gsp)
|
||||
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_TOP , struct nvkm_top , top)
|
||||
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_VFN , struct nvkm_vfn , vfn)
|
||||
@@ -29,7 +30,7 @@ NVKM_LAYOUT_INST(NVKM_SUBDEV_IOCTRL , struct nvkm_subdev , ioctrl, 3)
|
||||
NVKM_LAYOUT_ONCE(NVKM_SUBDEV_FLA , struct nvkm_subdev , fla)
|
||||
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_BSP , struct nvkm_engine , bsp)
|
||||
NVKM_LAYOUT_INST(NVKM_ENGINE_CE , struct nvkm_engine , ce, 10)
|
||||
NVKM_LAYOUT_INST(NVKM_ENGINE_CE , struct nvkm_engine , ce, 20)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_CIPHER , struct nvkm_engine , cipher)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_DISP , struct nvkm_disp , disp)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_DMAOBJ , struct nvkm_dma , dma)
|
||||
@@ -43,9 +44,9 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC , struct nvkm_engine , mspdec)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP , struct nvkm_engine , msppp)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSVLD , struct nvkm_engine , msvld)
|
||||
NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 8)
|
||||
NVKM_LAYOUT_INST(NVKM_ENGINE_NVENC , struct nvkm_nvenc , nvenc, 3)
|
||||
NVKM_LAYOUT_INST(NVKM_ENGINE_NVENC , struct nvkm_nvenc , nvenc, 4)
|
||||
NVKM_LAYOUT_INST(NVKM_ENGINE_NVJPG , struct nvkm_engine , nvjpg, 8)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_OFA , struct nvkm_engine , ofa)
|
||||
NVKM_LAYOUT_INST(NVKM_ENGINE_OFA , struct nvkm_engine , ofa, 2)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC , struct nvkm_engine , sec)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC2 , struct nvkm_sec2 , sec2)
|
||||
NVKM_LAYOUT_ONCE(NVKM_ENGINE_SW , struct nvkm_sw , sw)
|
||||
|
||||
@@ -87,5 +87,4 @@ int gp102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
|
||||
int gv100_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
|
||||
int tu102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
|
||||
int ga102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
|
||||
int ad102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **);
|
||||
#endif
|
||||
|
||||
@@ -78,9 +78,6 @@ struct nvkm_fifo {
|
||||
struct {
|
||||
struct nvkm_memory *mem;
|
||||
struct nvkm_vma *bar1;
|
||||
|
||||
struct mutex mutex;
|
||||
struct list_head list;
|
||||
} userd;
|
||||
|
||||
struct {
|
||||
|
||||
@@ -55,5 +55,4 @@ int gp10b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct n
|
||||
int gv100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
|
||||
int tu102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
|
||||
int ga102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
|
||||
int ad102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
|
||||
#endif
|
||||
|
||||
@@ -13,7 +13,5 @@ struct nvkm_nvdec {
|
||||
|
||||
int gm107_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
|
||||
int tu102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
|
||||
int ga100_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
|
||||
int ga102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
|
||||
int ad102_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
|
||||
#endif
|
||||
|
||||
@@ -13,6 +13,4 @@ struct nvkm_nvenc {
|
||||
|
||||
int gm107_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
|
||||
int tu102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
|
||||
int ga102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
|
||||
int ad102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvenc **);
|
||||
#endif
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
#ifndef __NVKM_NVJPG_H__
|
||||
#define __NVKM_NVJPG_H__
|
||||
#include <core/engine.h>
|
||||
|
||||
int ga100_nvjpg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
|
||||
int ad102_nvjpg_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
|
||||
#endif
|
||||
@@ -1,9 +0,0 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
#ifndef __NVKM_OFA_H__
|
||||
#define __NVKM_OFA_H__
|
||||
#include <core/engine.h>
|
||||
|
||||
int ga100_ofa_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
|
||||
int ga102_ofa_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
|
||||
int ad102_ofa_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
|
||||
#endif
|
||||
@@ -102,6 +102,9 @@ int gv100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct n
|
||||
int tu102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
|
||||
int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
|
||||
int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
|
||||
int gh100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
|
||||
int gb100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
|
||||
int gb202_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
|
||||
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bios/ramcfg.h>
|
||||
|
||||
24
drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h
Normal file
24
drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h
Normal file
@@ -0,0 +1,24 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
#ifndef __NVKM_FSP_H__
|
||||
#define __NVKM_FSP_H__
|
||||
#include <core/subdev.h>
|
||||
#include <core/falcon.h>
|
||||
|
||||
struct nvkm_fsp {
|
||||
const struct nvkm_fsp_func *func;
|
||||
struct nvkm_subdev subdev;
|
||||
|
||||
struct nvkm_falcon falcon;
|
||||
};
|
||||
|
||||
bool nvkm_fsp_verify_gsp_fmc(struct nvkm_fsp *, u32 hash_size, u32 pkey_size, u32 sig_size);
|
||||
int nvkm_fsp_boot_gsp_fmc(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool resume,
|
||||
u64 img_addr, const u8 *hash, const u8 *pkey, const u8 *sig);
|
||||
|
||||
int gh100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
|
||||
int gb100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
|
||||
int gb202_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
|
||||
#endif
|
||||
@@ -17,6 +17,9 @@ struct nvkm_gsp_mem {
|
||||
dma_addr_t addr;
|
||||
};
|
||||
|
||||
int nvkm_gsp_mem_ctor(struct nvkm_gsp *, size_t size, struct nvkm_gsp_mem *);
|
||||
void nvkm_gsp_mem_dtor(struct nvkm_gsp_mem *);
|
||||
|
||||
struct nvkm_gsp_radix3 {
|
||||
struct nvkm_gsp_mem lvl0;
|
||||
struct nvkm_gsp_mem lvl1;
|
||||
@@ -65,6 +68,9 @@ struct nvkm_gsp {
|
||||
const struct firmware *load;
|
||||
const struct firmware *unload;
|
||||
} booter;
|
||||
|
||||
const struct firmware *fmc;
|
||||
|
||||
const struct firmware *bl;
|
||||
const struct firmware *rm;
|
||||
} fws;
|
||||
@@ -110,6 +116,15 @@ struct nvkm_gsp {
|
||||
struct nvkm_falcon_fw unload;
|
||||
} booter;
|
||||
|
||||
struct {
|
||||
struct nvkm_gsp_mem fw;
|
||||
u8 *hash;
|
||||
u8 *pkey;
|
||||
u8 *sig;
|
||||
|
||||
struct nvkm_gsp_mem args;
|
||||
} fmc;
|
||||
|
||||
struct {
|
||||
struct nvkm_gsp_mem fw;
|
||||
u32 code_offset;
|
||||
@@ -130,6 +145,7 @@ struct nvkm_gsp {
|
||||
struct sg_table sgt;
|
||||
struct nvkm_gsp_radix3 radix3;
|
||||
struct nvkm_gsp_mem meta;
|
||||
struct sg_table fbsr;
|
||||
} sr;
|
||||
|
||||
struct {
|
||||
@@ -209,32 +225,7 @@ struct nvkm_gsp {
|
||||
u8 tpcs;
|
||||
} gr;
|
||||
|
||||
const struct nvkm_gsp_rm {
|
||||
void *(*rpc_get)(struct nvkm_gsp *, u32 fn, u32 argc);
|
||||
void *(*rpc_push)(struct nvkm_gsp *gsp, void *argv,
|
||||
enum nvkm_gsp_rpc_reply_policy policy, u32 repc);
|
||||
void (*rpc_done)(struct nvkm_gsp *gsp, void *repv);
|
||||
|
||||
void *(*rm_ctrl_get)(struct nvkm_gsp_object *, u32 cmd, u32 argc);
|
||||
int (*rm_ctrl_push)(struct nvkm_gsp_object *, void **argv, u32 repc);
|
||||
void (*rm_ctrl_done)(struct nvkm_gsp_object *, void *repv);
|
||||
|
||||
void *(*rm_alloc_get)(struct nvkm_gsp_object *, u32 oclass, u32 argc);
|
||||
void *(*rm_alloc_push)(struct nvkm_gsp_object *, void *argv);
|
||||
void (*rm_alloc_done)(struct nvkm_gsp_object *, void *repv);
|
||||
|
||||
int (*rm_free)(struct nvkm_gsp_object *);
|
||||
|
||||
int (*client_ctor)(struct nvkm_gsp *, struct nvkm_gsp_client *);
|
||||
void (*client_dtor)(struct nvkm_gsp_client *);
|
||||
|
||||
int (*device_ctor)(struct nvkm_gsp_client *, struct nvkm_gsp_device *);
|
||||
void (*device_dtor)(struct nvkm_gsp_device *);
|
||||
|
||||
int (*event_ctor)(struct nvkm_gsp_device *, u32 handle, u32 id,
|
||||
nvkm_gsp_event_func, struct nvkm_gsp_event *);
|
||||
void (*event_dtor)(struct nvkm_gsp_event *);
|
||||
} *rm;
|
||||
struct nvkm_rm *rm;
|
||||
|
||||
struct {
|
||||
struct mutex mutex;
|
||||
@@ -272,17 +263,19 @@ nvkm_gsp_rm(struct nvkm_gsp *gsp)
|
||||
return gsp && (gsp->fws.rm || gsp->fw.img);
|
||||
}
|
||||
|
||||
#include <rm/rm.h>
|
||||
|
||||
static inline void *
|
||||
nvkm_gsp_rpc_get(struct nvkm_gsp *gsp, u32 fn, u32 argc)
|
||||
{
|
||||
return gsp->rm->rpc_get(gsp, fn, argc);
|
||||
return gsp->rm->api->rpc->get(gsp, fn, argc);
|
||||
}
|
||||
|
||||
static inline void *
|
||||
nvkm_gsp_rpc_push(struct nvkm_gsp *gsp, void *argv,
|
||||
enum nvkm_gsp_rpc_reply_policy policy, u32 repc)
|
||||
{
|
||||
return gsp->rm->rpc_push(gsp, argv, policy, repc);
|
||||
return gsp->rm->api->rpc->push(gsp, argv, policy, repc);
|
||||
}
|
||||
|
||||
static inline void *
|
||||
@@ -311,19 +304,19 @@ nvkm_gsp_rpc_wr(struct nvkm_gsp *gsp, void *argv,
|
||||
static inline void
|
||||
nvkm_gsp_rpc_done(struct nvkm_gsp *gsp, void *repv)
|
||||
{
|
||||
gsp->rm->rpc_done(gsp, repv);
|
||||
gsp->rm->api->rpc->done(gsp, repv);
|
||||
}
|
||||
|
||||
static inline void *
|
||||
nvkm_gsp_rm_ctrl_get(struct nvkm_gsp_object *object, u32 cmd, u32 argc)
|
||||
{
|
||||
return object->client->gsp->rm->rm_ctrl_get(object, cmd, argc);
|
||||
return object->client->gsp->rm->api->ctrl->get(object, cmd, argc);
|
||||
}
|
||||
|
||||
static inline int
|
||||
nvkm_gsp_rm_ctrl_push(struct nvkm_gsp_object *object, void *argv, u32 repc)
|
||||
{
|
||||
return object->client->gsp->rm->rm_ctrl_push(object, argv, repc);
|
||||
return object->client->gsp->rm->api->ctrl->push(object, argv, repc);
|
||||
}
|
||||
|
||||
static inline void *
|
||||
@@ -354,7 +347,7 @@ nvkm_gsp_rm_ctrl_wr(struct nvkm_gsp_object *object, void *argv)
|
||||
static inline void
|
||||
nvkm_gsp_rm_ctrl_done(struct nvkm_gsp_object *object, void *repv)
|
||||
{
|
||||
object->client->gsp->rm->rm_ctrl_done(object, repv);
|
||||
object->client->gsp->rm->api->ctrl->done(object, repv);
|
||||
}
|
||||
|
||||
static inline void *
|
||||
@@ -369,7 +362,7 @@ nvkm_gsp_rm_alloc_get(struct nvkm_gsp_object *parent, u32 handle, u32 oclass, u3
|
||||
object->parent = parent;
|
||||
object->handle = handle;
|
||||
|
||||
argv = gsp->rm->rm_alloc_get(object, oclass, argc);
|
||||
argv = gsp->rm->api->alloc->get(object, oclass, argc);
|
||||
if (IS_ERR_OR_NULL(argv)) {
|
||||
object->client = NULL;
|
||||
return argv;
|
||||
@@ -381,7 +374,7 @@ nvkm_gsp_rm_alloc_get(struct nvkm_gsp_object *parent, u32 handle, u32 oclass, u3
|
||||
static inline void *
|
||||
nvkm_gsp_rm_alloc_push(struct nvkm_gsp_object *object, void *argv)
|
||||
{
|
||||
void *repv = object->client->gsp->rm->rm_alloc_push(object, argv);
|
||||
void *repv = object->client->gsp->rm->api->alloc->push(object, argv);
|
||||
|
||||
if (IS_ERR(repv))
|
||||
object->client = NULL;
|
||||
@@ -403,7 +396,7 @@ nvkm_gsp_rm_alloc_wr(struct nvkm_gsp_object *object, void *argv)
|
||||
static inline void
|
||||
nvkm_gsp_rm_alloc_done(struct nvkm_gsp_object *object, void *repv)
|
||||
{
|
||||
object->client->gsp->rm->rm_alloc_done(object, repv);
|
||||
object->client->gsp->rm->api->alloc->done(object, repv);
|
||||
}
|
||||
|
||||
static inline int
|
||||
@@ -421,39 +414,29 @@ nvkm_gsp_rm_alloc(struct nvkm_gsp_object *parent, u32 handle, u32 oclass, u32 ar
|
||||
static inline int
|
||||
nvkm_gsp_rm_free(struct nvkm_gsp_object *object)
|
||||
{
|
||||
if (object->client)
|
||||
return object->client->gsp->rm->rm_free(object);
|
||||
if (object->client) {
|
||||
int ret = object->client->gsp->rm->api->alloc->free(object);
|
||||
object->client = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int
|
||||
nvkm_gsp_client_ctor(struct nvkm_gsp *gsp, struct nvkm_gsp_client *client)
|
||||
{
|
||||
if (WARN_ON(!gsp->rm))
|
||||
return -ENOSYS;
|
||||
|
||||
return gsp->rm->client_ctor(gsp, client);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nvkm_gsp_client_dtor(struct nvkm_gsp_client *client)
|
||||
{
|
||||
if (client->gsp)
|
||||
client->gsp->rm->client_dtor(client);
|
||||
}
|
||||
int nvkm_gsp_client_ctor(struct nvkm_gsp *, struct nvkm_gsp_client *);
|
||||
void nvkm_gsp_client_dtor(struct nvkm_gsp_client *);
|
||||
|
||||
static inline int
|
||||
nvkm_gsp_device_ctor(struct nvkm_gsp_client *client, struct nvkm_gsp_device *device)
|
||||
{
|
||||
return client->gsp->rm->device_ctor(client, device);
|
||||
return client->gsp->rm->api->device->ctor(client, device);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nvkm_gsp_device_dtor(struct nvkm_gsp_device *device)
|
||||
{
|
||||
if (device->object.client)
|
||||
device->object.client->gsp->rm->device_dtor(device);
|
||||
device->object.client->gsp->rm->api->device->dtor(device);
|
||||
}
|
||||
|
||||
static inline int
|
||||
@@ -485,7 +468,9 @@ static inline int
|
||||
nvkm_gsp_device_event_ctor(struct nvkm_gsp_device *device, u32 handle, u32 id,
|
||||
nvkm_gsp_event_func func, struct nvkm_gsp_event *event)
|
||||
{
|
||||
return device->object.client->gsp->rm->event_ctor(device, handle, id, func, event);
|
||||
struct nvkm_rm *rm = device->object.client->gsp->rm;
|
||||
|
||||
return rm->api->device->event.ctor(device, handle, id, func, event);
|
||||
}
|
||||
|
||||
static inline void
|
||||
@@ -494,7 +479,7 @@ nvkm_gsp_event_dtor(struct nvkm_gsp_event *event)
|
||||
struct nvkm_gsp_device *device = event->device;
|
||||
|
||||
if (device)
|
||||
device->object.client->gsp->rm->event_dtor(event);
|
||||
device->object.client->gsp->rm->api->device->event.dtor(event);
|
||||
}
|
||||
|
||||
int nvkm_gsp_intr_stall(struct nvkm_gsp *, enum nvkm_subdev_type, int);
|
||||
@@ -505,5 +490,8 @@ int tu102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_
|
||||
int tu116_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
|
||||
int ga100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
|
||||
int ga102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
|
||||
int gh100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
|
||||
int ad102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
|
||||
int gb100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
|
||||
int gb202_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
|
||||
#endif
|
||||
|
||||
@@ -24,11 +24,6 @@ struct nvkm_instmem {
|
||||
struct nvkm_ramht *ramht;
|
||||
struct nvkm_memory *ramro;
|
||||
struct nvkm_memory *ramfc;
|
||||
|
||||
struct {
|
||||
struct sg_table fbsr;
|
||||
bool fbsr_valid;
|
||||
} rm;
|
||||
};
|
||||
|
||||
u32 nvkm_instmem_rd32(struct nvkm_instmem *, u32 addr);
|
||||
@@ -41,4 +36,5 @@ int nv04_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nv
|
||||
int nv40_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **);
|
||||
int nv50_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **);
|
||||
int gk20a_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **);
|
||||
int gh100_instmem_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_instmem **);
|
||||
#endif
|
||||
|
||||
@@ -8,7 +8,7 @@ struct nvkm_vma {
|
||||
struct list_head head;
|
||||
struct rb_node tree;
|
||||
u64 addr;
|
||||
u64 size:50;
|
||||
u64 size;
|
||||
bool mapref:1; /* PTs (de)referenced on (un)map (vs pre-allocated). */
|
||||
bool sparse:1; /* Unmapped PDEs/PTEs will not trigger MMU faults. */
|
||||
#define NVKM_VMA_PAGE_NONE 7
|
||||
@@ -73,6 +73,7 @@ struct nvkm_vmm {
|
||||
struct nvkm_gsp_object object;
|
||||
|
||||
struct nvkm_vma *rsvd;
|
||||
bool external;
|
||||
} rm;
|
||||
};
|
||||
|
||||
@@ -165,4 +166,5 @@ int gp100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
|
||||
int gp10b_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
|
||||
int gv100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
|
||||
int tu102_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
|
||||
int gh100_mmu_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_mmu **);
|
||||
#endif
|
||||
|
||||
@@ -50,6 +50,7 @@ int gf100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
|
||||
int gf106_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
|
||||
int gk104_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
|
||||
int gp100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
|
||||
int gh100_pci_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_pci **);
|
||||
|
||||
/* pcie functions */
|
||||
int nvkm_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8 width);
|
||||
|
||||
@@ -1,38 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_cl0000_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_cl0000_h__
|
||||
#include <nvrm/535.113.01/common/sdk/nvidia/inc/nvlimits.h>
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV01_ROOT (0x0U) /* finn: Evaluated from "NV0000_ALLOC_PARAMETERS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0000_ALLOC_PARAMETERS {
|
||||
NvHandle hClient; /* CORERM-2934: hClient must remain the first member until all allocations use these params */
|
||||
NvU32 processID;
|
||||
char processName[NV_PROC_NAME_MAX_LENGTH];
|
||||
} NV0000_ALLOC_PARAMETERS;
|
||||
|
||||
#endif
|
||||
@@ -1,38 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_cl0005_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_cl0005_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct NV0005_ALLOC_PARAMETERS {
|
||||
NvHandle hParentClient;
|
||||
NvHandle hSrcResource;
|
||||
|
||||
NvV32 hClass;
|
||||
NvV32 notifyIndex;
|
||||
NV_DECLARE_ALIGNED(NvP64 data, 8);
|
||||
} NV0005_ALLOC_PARAMETERS;
|
||||
|
||||
#endif
|
||||
@@ -1,43 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_cl0080_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_cl0080_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV01_DEVICE_0 (0x80U) /* finn: Evaluated from "NV0080_ALLOC_PARAMETERS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0080_ALLOC_PARAMETERS {
|
||||
NvU32 deviceId;
|
||||
NvHandle hClientShare;
|
||||
NvHandle hTargetClient;
|
||||
NvHandle hTargetDevice;
|
||||
NvV32 flags;
|
||||
NV_DECLARE_ALIGNED(NvU64 vaSpaceSize, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 vaStartInternal, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 vaLimitInternal, 8);
|
||||
NvV32 vaMode;
|
||||
} NV0080_ALLOC_PARAMETERS;
|
||||
|
||||
#endif
|
||||
@@ -1,35 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_cl2080_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_cl2080_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV20_SUBDEVICE_0 (0x2080U) /* finn: Evaluated from "NV2080_ALLOC_PARAMETERS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_ALLOC_PARAMETERS {
|
||||
NvU32 subDeviceId;
|
||||
} NV2080_ALLOC_PARAMETERS;
|
||||
|
||||
#endif
|
||||
@@ -1,62 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_cl2080_notification_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_cl2080_notification_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV2080_NOTIFIERS_HOTPLUG (1)
|
||||
|
||||
#define NV2080_NOTIFIERS_DP_IRQ (7)
|
||||
|
||||
#define NV2080_ENGINE_TYPE_GRAPHICS (0x00000001)
|
||||
#define NV2080_ENGINE_TYPE_GR0 NV2080_ENGINE_TYPE_GRAPHICS
|
||||
|
||||
#define NV2080_ENGINE_TYPE_COPY0 (0x00000009)
|
||||
|
||||
#define NV2080_ENGINE_TYPE_BSP (0x00000013)
|
||||
#define NV2080_ENGINE_TYPE_NVDEC0 NV2080_ENGINE_TYPE_BSP
|
||||
|
||||
#define NV2080_ENGINE_TYPE_MSENC (0x0000001b)
|
||||
#define NV2080_ENGINE_TYPE_NVENC0 NV2080_ENGINE_TYPE_MSENC /* Mutually exclusive alias */
|
||||
|
||||
#define NV2080_ENGINE_TYPE_SW (0x00000022)
|
||||
|
||||
#define NV2080_ENGINE_TYPE_SEC2 (0x00000026)
|
||||
|
||||
#define NV2080_ENGINE_TYPE_NVJPG (0x0000002b)
|
||||
#define NV2080_ENGINE_TYPE_NVJPEG0 NV2080_ENGINE_TYPE_NVJPG
|
||||
|
||||
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
|
||||
|
||||
typedef struct {
|
||||
NvU32 plugDisplayMask;
|
||||
NvU32 unplugDisplayMask;
|
||||
} Nv2080HotplugNotification;
|
||||
|
||||
typedef struct Nv2080DpIrqNotificationRec {
|
||||
NvU32 displayId;
|
||||
} Nv2080DpIrqNotification;
|
||||
|
||||
#endif
|
||||
@@ -1,33 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_cl84a0_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_cl84a0_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV01_MEMORY_LIST_SYSTEM (0x00000081)
|
||||
|
||||
#define NV01_MEMORY_LIST_FBMEM (0x00000082)
|
||||
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_cl90f1_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_cl90f1_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2011 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define FERMI_VASPACE_A (0x000090f1)
|
||||
|
||||
#endif
|
||||
@@ -1,34 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_class_clc0b5sw_h__
|
||||
#define __src_common_sdk_nvidia_inc_class_clc0b5sw_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct NVC0B5_ALLOCATION_PARAMETERS {
|
||||
NvU32 version;
|
||||
NvU32 engineType;
|
||||
} NVC0B5_ALLOCATION_PARAMETERS;
|
||||
|
||||
#endif
|
||||
@@ -1,39 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073common_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073common_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DSC_CAP_PARAMS {
|
||||
NvBool bDscSupported;
|
||||
NvU32 encoderColorFormatMask;
|
||||
NvU32 lineBufferSizeKB;
|
||||
NvU32 rateBufferSizeKB;
|
||||
NvU32 bitsPerPixelPrecision;
|
||||
NvU32 maxNumHztSlices;
|
||||
NvU32 lineBufferBitDepth;
|
||||
} NV0073_CTRL_CMD_DSC_CAP_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,166 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dfp_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dfp_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_DFP_GET_INFO (0x731140U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_GET_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 flags;
|
||||
NvU32 flags2;
|
||||
} NV0073_CTRL_DFP_GET_INFO_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_DFP_FLAGS_SIGNAL 2:0
|
||||
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_TMDS (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_LVDS (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_SDI (0x00000002U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DISPLAYPORT (0x00000003U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_DSI (0x00000004U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_SIGNAL_WRBK (0x00000005U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LANE 5:3
|
||||
#define NV0073_CTRL_DFP_FLAGS_LANE_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LANE_SINGLE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LANE_DUAL (0x00000002U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LANE_QUAD (0x00000003U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LANE_OCT (0x00000004U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LIMIT 6:6
|
||||
#define NV0073_CTRL_DFP_FLAGS_LIMIT_DISABLE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LIMIT_60HZ_RR (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER 7:7
|
||||
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_NORMAL (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_SLI_SCALER_DISABLE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE 8:8
|
||||
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_HDMI_CAPABLE_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE 9:9
|
||||
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_RANGE_LIMITED_CAPABLE_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE 10:10
|
||||
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_RANGE_AUTO_CAPABLE_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE 11:11
|
||||
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR422_CAPABLE_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE 12:12
|
||||
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_FORMAT_YCBCR444_CAPABLE_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED 14:14
|
||||
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_HDMI_ALLOWED_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT 15:15
|
||||
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_EMBEDDED_DISPLAYPORT_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT 16:16
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_CONSTRAINT_PREFER_RBR (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW 19:17
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_1_62GBPS (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_2_70GBPS (0x00000002U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_5_40GBPS (0x00000003U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_LINK_BW_8_10GBPS (0x00000004U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LINK 21:20
|
||||
#define NV0073_CTRL_DFP_FLAGS_LINK_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LINK_SINGLE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_LINK_DUAL (0x00000002U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID 22:22
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_FORCE_RM_EDID_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID 24:23
|
||||
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_A (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_B (0x00000002U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DSI_DEVICE_ID_DSI_GANGED (0x00000003U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED 25:25
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_POST_CURSOR2_DISABLED_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DP_PHY_REPEATER_COUNT 29:26
|
||||
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30
|
||||
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DFP_SET_ELD_AUDIO_CAPS (0x731144U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER 96U
|
||||
|
||||
typedef struct NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 numELDSize;
|
||||
NvU8 bufferELD[NV0073_CTRL_DFP_ELD_AUDIO_CAPS_ELD_BUFFER];
|
||||
NvU32 maxFreqSupported;
|
||||
NvU32 ctrl;
|
||||
NvU32 deviceEntry;
|
||||
} NV0073_CTRL_DFP_SET_ELD_AUDIO_CAP_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD 0:0
|
||||
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_PD_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV 1:1
|
||||
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_ELD_AUDIO_CAPS_CTRL_ELDV_TRUE (0x00000001U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DFP_SET_AUDIO_ENABLE (0x731150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvBool enable;
|
||||
} NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS;
|
||||
|
||||
typedef NvU32 NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG;
|
||||
|
||||
typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_INFO {
|
||||
NvU32 displayMask;
|
||||
NvU32 sorType;
|
||||
} NV0073_CTRL_DFP_ASSIGN_SOR_INFO;
|
||||
|
||||
#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR (0x731152U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DFP_INTERFACE_ID << 8) | NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS 4U
|
||||
|
||||
typedef struct NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU8 sorExcludeMask;
|
||||
NvU32 slaveDisplayId;
|
||||
NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG forceSublinkConfig;
|
||||
NvBool bIs2Head1Or;
|
||||
NvU32 sorAssignList[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS];
|
||||
NV0073_CTRL_DFP_ASSIGN_SOR_INFO sorAssignListWithTag[NV0073_CTRL_CMD_DFP_ASSIGN_SOR_MAX_SORS];
|
||||
NvU8 reservedSorMask;
|
||||
NvU32 flags;
|
||||
} NV0073_CTRL_DFP_ASSIGN_SOR_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO 0:0
|
||||
#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_OPTIMAL (0x00000001U)
|
||||
#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_AUDIO_DEFAULT (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE 1:1
|
||||
#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DFP_ASSIGN_SOR_FLAGS_ACTIVE_SOR_NOT_AUDIO_CAPABLE_YES (0x00000001U)
|
||||
|
||||
#endif
|
||||
@@ -1,335 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dp_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073dp_h__
|
||||
#include <nvrm/535.113.01/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073common.h>
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_AUXCH_CTRL (0x731341U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_AUXCH_CTRL_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE 16U
|
||||
|
||||
typedef struct NV0073_CTRL_DP_AUXCH_CTRL_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvBool bAddrOnly;
|
||||
NvU32 cmd;
|
||||
NvU32 addr;
|
||||
NvU8 data[NV0073_CTRL_DP_AUXCH_MAX_DATA_SIZE];
|
||||
NvU32 size;
|
||||
NvU32 replyType;
|
||||
NvU32 retryTimeMs;
|
||||
} NV0073_CTRL_DP_AUXCH_CTRL_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_TYPE 3:3
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_I2C (0x00000000U)
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_TYPE_AUX (0x00000001U)
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT 2:2
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_I2C_MOT_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE 1:0
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_READ (0x00000001U)
|
||||
#define NV0073_CTRL_DP_AUXCH_CMD_REQ_TYPE_WRITE_STATUS (0x00000002U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_CTRL (0x731343U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_CTRL_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_DP_CTRL_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 cmd;
|
||||
NvU32 data;
|
||||
NvU32 err;
|
||||
NvU32 retryTimeMs;
|
||||
NvU32 eightLaneDpcdBaseAddr;
|
||||
} NV0073_CTRL_DP_CTRL_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT 0:0
|
||||
#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_SET_LANE_COUNT_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_SET_LINK_BW 1:1
|
||||
#define NV0073_CTRL_DP_CMD_SET_LINK_BW_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_SET_LINK_BW_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD 2:2
|
||||
#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_DISABLE_DOWNSPREAD_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_UNUSED 3:3
|
||||
#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE 4:4
|
||||
#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_SINGLE_STREAM (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_SET_FORMAT_MODE_MULTI_STREAM (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING 5:5
|
||||
#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_FAST_LINK_TRAINING_YES (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING 6:6
|
||||
#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_NO_LINK_TRAINING_YES (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING 7:7
|
||||
#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_SET_ENHANCED_FRAMING_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING 8:8
|
||||
#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_DEFAULT (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_USE_DOWNSPREAD_SETTING_FORCE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING 9:9
|
||||
#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_SKIP_HW_PROGRAMMING_YES (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED 10:10
|
||||
#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_POST_LT_ADJ_REQ_GRANTED_YES (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING 12:11
|
||||
#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_DONOT_TOGGLE_TRANSMISSION (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_FAKE_LINK_TRAINING_TOGGLE_TRANSMISSION_ON (0x00000002U)
|
||||
#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER 13:13
|
||||
#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_TRAIN_PHY_REPEATER_YES (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG 14:14
|
||||
#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_FALLBACK_CONFIG_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_FEC 15:15
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_FEC_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_FEC_TRUE (0x00000001U)
|
||||
|
||||
#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST 29:29
|
||||
#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_BANDWIDTH_TEST_YES (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE 30:30
|
||||
#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_LINK_CONFIG_CHECK_DISABLE_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG 31:31
|
||||
#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_DISABLE_LINK_CONFIG_TRUE (0x00000001U)
|
||||
|
||||
#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT 4:0
|
||||
#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_0 (0x00000000U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_1 (0x00000001U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_2 (0x00000002U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_4 (0x00000004U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LANE_COUNT_8 (0x00000008U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW 15:8
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_1_62GBPS (0x00000006U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_16GBPS (0x00000008U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_43GBPS (0x00000009U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_2_70GBPS (0x0000000AU)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_3_24GBPS (0x0000000CU)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_4_32GBPS (0x00000010U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_5_40GBPS (0x00000014U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_LINK_BW_8_10GBPS (0x0000001EU)
|
||||
#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING 18:18
|
||||
#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_NO (0x00000000U)
|
||||
#define NV0073_CTRL_DP_DATA_SET_ENHANCED_FRAMING_YES (0x00000001U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET 22:19
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_SINK (0x00000000U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_0 (0x00000001U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_1 (0x00000002U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_2 (0x00000003U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_3 (0x00000004U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_4 (0x00000005U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_5 (0x00000006U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_6 (0x00000007U)
|
||||
#define NV0073_CTRL_DP_DATA_TARGET_PHY_REPEATER_7 (0x00000008U)
|
||||
|
||||
#define NV0073_CTRL_MAX_LANES 8U
|
||||
|
||||
typedef struct NV0073_CTRL_DP_LANE_DATA_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 numLanes;
|
||||
NvU32 data[NV0073_CTRL_MAX_LANES];
|
||||
} NV0073_CTRL_DP_LANE_DATA_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS 1:0
|
||||
#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL1 (0x00000001U)
|
||||
#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL2 (0x00000002U)
|
||||
#define NV0073_CTRL_DP_LANE_DATA_PREEMPHASIS_LEVEL3 (0x00000003U)
|
||||
#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT 3:2
|
||||
#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL0 (0x00000000U)
|
||||
#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL1 (0x00000001U)
|
||||
#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL2 (0x00000002U)
|
||||
#define NV0073_CTRL_DP_LANE_DATA_DRIVECURRENT_LEVEL3 (0x00000003U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_SET_LANE_DATA (0x731346U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_LANE_DATA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 mute;
|
||||
} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID (0x73135bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 preferredDisplayId;
|
||||
|
||||
NvBool force;
|
||||
NvBool useBFM;
|
||||
|
||||
NvU32 displayIdAssigned;
|
||||
NvU32 allDisplayMask;
|
||||
} NV0073_CTRL_CMD_DP_TOPOLOGY_ALLOCATE_DISPLAYID_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID (0x73135cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
} NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_CONFIG_STREAM (0x731362U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 head;
|
||||
NvU32 sorIndex;
|
||||
NvU32 dpLink;
|
||||
|
||||
NvBool bEnableOverride;
|
||||
NvBool bMST;
|
||||
NvU32 singleHeadMultistreamMode;
|
||||
NvU32 hBlankSym;
|
||||
NvU32 vBlankSym;
|
||||
NvU32 colorFormat;
|
||||
NvBool bEnableTwoHeadOneOr;
|
||||
|
||||
struct {
|
||||
NvU32 slotStart;
|
||||
NvU32 slotEnd;
|
||||
NvU32 PBN;
|
||||
NvU32 Timeslice;
|
||||
NvBool sendACT; // deprecated -Use NV0073_CTRL_CMD_DP_SEND_ACT
|
||||
NvU32 singleHeadMSTPipeline;
|
||||
NvBool bEnableAudioOverRightPanel;
|
||||
} MST;
|
||||
|
||||
struct {
|
||||
NvBool bEnhancedFraming;
|
||||
NvU32 tuSize;
|
||||
NvU32 waterMark;
|
||||
NvU32 actualPclkHz; // deprecated -Use MvidWarParams
|
||||
NvU32 linkClkFreqHz; // deprecated -Use MvidWarParams
|
||||
NvBool bEnableAudioOverRightPanel;
|
||||
struct {
|
||||
NvU32 activeCnt;
|
||||
NvU32 activeFrac;
|
||||
NvU32 activePolarity;
|
||||
NvBool mvidWarEnabled;
|
||||
struct {
|
||||
NvU32 actualPclkHz;
|
||||
NvU32 linkClkFreqHz;
|
||||
} MvidWarParams;
|
||||
} Legacy;
|
||||
} SST;
|
||||
} NV0073_CTRL_CMD_DP_CONFIG_STREAM_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT (0x731365U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
} NV0073_CTRL_CMD_DP_SET_MANUAL_DISPLAYPORT_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS (0x731369U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS_MESSAGE_ID (0x69U)
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 sorIndex;
|
||||
NvU32 maxLinkRate;
|
||||
NvU32 dpVersionsSupported;
|
||||
NvU32 UHBRSupported;
|
||||
NvBool bIsMultistreamSupported;
|
||||
NvBool bIsSCEnabled;
|
||||
NvBool bHasIncreasedWatermarkLimits;
|
||||
NvBool bIsPC2Disabled;
|
||||
NvBool isSingleHeadMSTSupported;
|
||||
NvBool bFECSupported;
|
||||
NvBool bIsTrainPhyRepeater;
|
||||
NvBool bOverrideLinkBw;
|
||||
NV0073_CTRL_CMD_DSC_CAP_PARAMS DSC;
|
||||
} NV0073_CTRL_CMD_DP_GET_CAPS_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2 0:0
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_NO (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_2_YES (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4 1:1
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_NO (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DP_VERSIONS_SUPPORTED_DP1_4_YES (0x00000001U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE 2:0
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_1_62 (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_2_70 (0x00000002U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_5_40 (0x00000003U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_MAX_LINK_RATE_8_10 (0x00000004U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_RGB (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_444 (0x00000002U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_422 (0x00000004U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_ENCODER_COLOR_FORMAT_Y_CB_CR_NATIVE_420 (0x00000008U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_16 (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_8 (0x00000002U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_4 (0x00000003U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1_2 (0x00000004U)
|
||||
#define NV0073_CTRL_CMD_DP_GET_CAPS_DSC_BITS_PER_PIXEL_PRECISION_1 (0x00000005U)
|
||||
|
||||
#define NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES (0x731377U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES 8U
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS {
|
||||
// In
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU16 linkRateTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES];
|
||||
|
||||
// Out
|
||||
NvU8 linkBwTbl[NV0073_CTRL_DP_MAX_INDEXED_LINK_RATES];
|
||||
NvU8 linkBwCount;
|
||||
} NV0073_CTRL_CMD_DP_CONFIG_INDEXED_LINK_RATES_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE 3:0
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_BEGIN (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHALLENGE (0x00000001U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_MONITOR_ENABLE_CHECK (0x00000002U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_BEGIN (0x00000003U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHALLENGE (0x00000004U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_DRIVER_ENABLE_CHECK (0x00000005U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_RESET_MONITOR (0x00000006U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_INIT_PUBLIC_INFO (0x00000007U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_GET_PUBLIC_INFO (0x00000008U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_CMD_STAGE_STATUS_CHECK (0x00000009U)
|
||||
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_OK (0x00000000U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_PENDING (0x80000001U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_READ_ERROR (0x80000002U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_WRITE_ERROR (0x80000003U)
|
||||
#define NV0073_CTRL_DP_CMD_ENABLE_VRR_STATUS_DEVICE_ERROR (0x80000004U)
|
||||
|
||||
#endif
|
||||
@@ -1,216 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073specific_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073specific_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_GET_EDID_V2 (0x730245U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES 2048U
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 bufferSize;
|
||||
NvU32 flags;
|
||||
NvU8 edidBuffer[NV0073_CTRL_SPECIFIC_GET_EDID_MAX_EDID_BYTES];
|
||||
} NV0073_CTRL_SPECIFIC_GET_EDID_V2_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_GET_CONNECTOR_DATA (0x730250U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_MAX_CONNECTORS 4U
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 flags;
|
||||
NvU32 DDCPartners;
|
||||
NvU32 count;
|
||||
struct {
|
||||
NvU32 index;
|
||||
NvU32 type;
|
||||
NvU32 location;
|
||||
} data[NV0073_CTRL_MAX_CONNECTORS];
|
||||
NvU32 platform;
|
||||
} NV0073_CTRL_SPECIFIC_GET_CONNECTOR_DATA_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_ENABLE (0x730273U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS {
|
||||
NvU8 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU8 enable;
|
||||
} NV0073_CTRL_SPECIFIC_SET_HDMI_ENABLE_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM (0x730275U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS {
|
||||
NvU8 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU8 mute;
|
||||
} NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_AUDIO_MUTESTREAM_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_GET_ALL_HEAD_MASK (0x730287U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 headMask;
|
||||
} NV0073_CTRL_SPECIFIC_GET_ALL_HEAD_MASK_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET (0x730288U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_SET_OD_MAX_PACKET_SIZE 36U
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 transmitControl;
|
||||
NvU32 packetSize;
|
||||
NvU32 targetHead;
|
||||
NvBool bUsePsrHeadforSdp;
|
||||
NvU8 aPacket[NV0073_CTRL_SET_OD_MAX_PACKET_SIZE];
|
||||
} NV0073_CTRL_SPECIFIC_SET_OD_PACKET_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE 0:0
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_NO (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ENABLE_YES (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME 1:1
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_DISABLE (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_OTHER_FRAME_ENABLE (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME 2:2
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_DISABLE (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SINGLE_FRAME_ENABLE (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK 3:3
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_DISABLE (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_ON_HBLANK_ENABLE (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE 4:4
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_DISABLE (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_IMMEDIATE_ENABLE (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT 5:5
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_SW_CONTROLLED (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_VIDEO_FMT_HW_CONTROLLED (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY 6:6
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_FALSE (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_STEREO_POLARITY_TRUE (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING 7:7
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_FALSE (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_SET_SELF_REFRESH_SETTING_TRUE (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE 9:8
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME0 (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_GEN_INFOFRAME_MODE_INFOFRAME1 (0x0000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE 31:31
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_NO (0x0000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_SET_OD_PACKET_TRANSMIT_CONTROL_RESERVED_LEGACY_MODE_YES (0x0000001U)
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO (0x73028bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 index;
|
||||
NvU32 type;
|
||||
NvU32 protocol;
|
||||
NvU32 ditherType;
|
||||
NvU32 ditherAlgo;
|
||||
NvU32 location;
|
||||
NvU32 rootPortId;
|
||||
NvU32 dcbIndex;
|
||||
NV_DECLARE_ALIGNED(NvU64 vbiosAddress, 8);
|
||||
NvBool bIsLitByVbios;
|
||||
NvBool bIsDispDynamic;
|
||||
} NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_OR_TYPE_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_TYPE_DAC (0x00000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_TYPE_SOR (0x00000002U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_TYPE_PIOR (0x00000003U)
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_OR_TYPE_DSI (0x00000005U)
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DAC_RGB_CRT (0x00000000U)
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS (0x00000005U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A (0x00000008U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B (0x00000009U)
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DSI (0x00000010U)
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_DSI (0x00000011U)
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_PIOR_EXT_TMDS_ENC (0x00000000U)
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_OR_PROTOCOL_UNKNOWN (0xFFFFFFFFU)
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS (0x730291U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_GET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 brightness;
|
||||
NvBool bUncalibrated;
|
||||
} NV0073_CTRL_SPECIFIC_BACKLIGHT_BRIGHTNESS_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS (0x730292U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_BACKLIGHT_BRIGHTNESS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS (0x730293U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SPECIFIC_INTERFACE_ID << 8) | NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayId;
|
||||
NvU32 caps;
|
||||
} NV0073_CTRL_SPECIFIC_SET_HDMI_SINK_CAPS_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED 0:0
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_GT_340MHZ_CLOCK_SUPPORTED_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED 1:1
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_LTE_340MHZ_SCRAMBLING_SUPPORTED_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED 2:2
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_SCDC_SUPPORTED_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED 5:3
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED 6:6
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_FALSE (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_12_SUPPORTED_TRUE (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED 9:7
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_NONE (0x00000000U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_3G (0x00000001U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_3LANES_6G (0x00000002U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_6G (0x00000003U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_8G (0x00000004U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_10G (0x00000005U)
|
||||
#define NV0073_CTRL_CMD_SPECIFIC_SET_HDMI_SINK_CAPS_DSC_MAX_FRL_RATE_SUPPORTED_4LANES_12G (0x00000006U)
|
||||
|
||||
#endif
|
||||
@@ -1,65 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073system_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0073_ctrl0073system_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_SYSTEM_GET_NUM_HEADS (0x730102U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 flags;
|
||||
NvU32 numHeads;
|
||||
} NV0073_CTRL_SYSTEM_GET_NUM_HEADS_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED (0x730120U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 displayMask;
|
||||
NvU32 displayMaskDDC;
|
||||
} NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SYSTEM_GET_CONNECT_STATE (0x730122U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 flags;
|
||||
NvU32 displayMask;
|
||||
NvU32 retryTimeMs;
|
||||
} NV0073_CTRL_SYSTEM_GET_CONNECT_STATE_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_CMD_SYSTEM_GET_ACTIVE (0x730126U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 head;
|
||||
NvU32 flags;
|
||||
NvU32 displayId;
|
||||
} NV0073_CTRL_SYSTEM_GET_ACTIVE_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_SYSTEM_ACPI_ID_MAP_MAX_DISPLAYS (16U)
|
||||
|
||||
#endif
|
||||
@@ -1,48 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0080_ctrl0080gpu_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0080_ctrl0080gpu_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS {
|
||||
NvU32 totalVFs;
|
||||
NvU32 firstVfOffset;
|
||||
NvU32 vfFeatureMask;
|
||||
NV_DECLARE_ALIGNED(NvU64 FirstVFBar0Address, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 FirstVFBar1Address, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 FirstVFBar2Address, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 bar0Size, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 bar1Size, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 bar2Size, 8);
|
||||
NvBool b64bitBar0;
|
||||
NvBool b64bitBar1;
|
||||
NvBool b64bitBar2;
|
||||
NvBool bSriovEnabled;
|
||||
NvBool bSriovHeavyEnabled;
|
||||
NvBool bEmulateVFBar0TlbInvalidationRegister;
|
||||
NvBool bClientRmAllocatedCtxBuffer;
|
||||
} NV0080_CTRL_GPU_GET_SRIOV_CAPS_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl0080_ctrl0080gr_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl0080_ctrl0080gr_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV0080_CTRL_GR_CAPS_TBL_SIZE 23
|
||||
|
||||
#endif
|
||||
@@ -1,40 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080bios_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080bios_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS {
|
||||
NvU32 BoardID;
|
||||
char chipSKU[4];
|
||||
char chipSKUMod[2];
|
||||
char project[5];
|
||||
char projectSKU[5];
|
||||
char CDP[6];
|
||||
char projectSKUMod[2];
|
||||
NvU32 businessCycle;
|
||||
} NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,35 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080ce_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080ce_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS {
|
||||
NvU32 size;
|
||||
} NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_CE_GET_FAULT_METHOD_BUFFER_SIZE (0x20802a08) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#endif
|
||||
@@ -1,41 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080event_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080event_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION (0x20800301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS {
|
||||
NvU32 event;
|
||||
NvU32 action;
|
||||
NvBool bNotifyState;
|
||||
NvU32 info32;
|
||||
NvU16 info16;
|
||||
} NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT (0x00000002)
|
||||
|
||||
#endif
|
||||
@@ -1,51 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080fb_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080fb_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES 17U
|
||||
|
||||
typedef NvBool NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MEM_TYPES];
|
||||
|
||||
typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO {
|
||||
NV_DECLARE_ALIGNED(NvU64 base, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 limit, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 reserved, 8);
|
||||
NvU32 performance;
|
||||
NvBool supportCompressed;
|
||||
NvBool supportISO;
|
||||
NvBool bProtected;
|
||||
NV2080_CTRL_CMD_FB_GET_FB_REGION_SURFACE_MEM_TYPE_FLAG blackList;
|
||||
} NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO;
|
||||
|
||||
#define NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES 16U
|
||||
|
||||
typedef struct NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS {
|
||||
NvU32 numFBRegions;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_CMD_FB_GET_FB_REGION_FB_REGION_INFO fbRegion[NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_MAX_ENTRIES], 8);
|
||||
} NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,52 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080fifo_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080fifo_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_FIFO_GET_DEVICE_INFO_TABLE (0x20801112) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES 32
|
||||
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES 16
|
||||
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA 2
|
||||
#define NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN 16
|
||||
|
||||
typedef struct NV2080_CTRL_FIFO_DEVICE_ENTRY {
|
||||
NvU32 engineData[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_DATA_TYPES];
|
||||
NvU32 pbdmaIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
|
||||
NvU32 pbdmaFaultIds[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_PBDMA];
|
||||
NvU32 numPbdmas;
|
||||
char engineName[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_ENGINE_MAX_NAME_LEN];
|
||||
} NV2080_CTRL_FIFO_DEVICE_ENTRY;
|
||||
|
||||
typedef struct NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS {
|
||||
NvU32 baseIndex;
|
||||
NvU32 numEntries;
|
||||
NvBool bMore;
|
||||
// C form: NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
|
||||
NV2080_CTRL_FIFO_DEVICE_ENTRY entries[NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_MAX_ENTRIES];
|
||||
} NV2080_CTRL_FIFO_GET_DEVICE_INFO_TABLE_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,100 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080gpu_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080gpu_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV2080_GPU_MAX_NAME_STRING_LENGTH (0x0000040U)
|
||||
|
||||
#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_0 (0x00000000U)
|
||||
|
||||
#define NV2080_CTRL_GPU_SET_POWER_STATE_GPU_LEVEL_3 (0x00000003U)
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY {
|
||||
NV_DECLARE_ALIGNED(NvU64 gpuPhysAddr, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 gpuVirtAddr, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 size, 8);
|
||||
NvU32 physAttr;
|
||||
NvU16 bufferId;
|
||||
NvU8 bInitialize;
|
||||
NvU8 bNonmapped;
|
||||
} NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY;
|
||||
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_MAIN 0U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PM 1U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PATCH 2U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_BUFFER_BUNDLE_CB 3U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PAGEPOOL 4U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_ATTRIBUTE_CB 5U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_RTV_CB_GLOBAL 6U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_POOL 7U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GFXP_CTRL_BLK 8U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_FECS_EVENT 9U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_PRIV_ACCESS_MAP 10U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_UNRESTRICTED_PRIV_ACCESS_MAP 11U
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ID_GLOBAL_PRIV_ACCESS_MAP 12U
|
||||
|
||||
#define NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES 16U
|
||||
|
||||
#define NV2080_CTRL_CMD_GPU_PROMOTE_CTX (0x2080012bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS {
|
||||
NvU32 engineType;
|
||||
NvHandle hClient;
|
||||
NvU32 ChID;
|
||||
NvHandle hChanClient;
|
||||
NvHandle hObject;
|
||||
NvHandle hVirtMemory;
|
||||
NV_DECLARE_ALIGNED(NvU64 virtAddress, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 size, 8);
|
||||
NvU32 entryCount;
|
||||
// C form: NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES];
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_GPU_PROMOTE_CTX_BUFFER_ENTRY promoteEntry[NV2080_CTRL_GPU_PROMOTE_CONTEXT_MAX_ENTRIES], 8);
|
||||
} NV2080_CTRL_GPU_PROMOTE_CTX_PARAMS;
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS {
|
||||
NvU32 gpcMask;
|
||||
} NV2080_CTRL_GPU_GET_FERMI_GPC_INFO_PARAMS;
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS {
|
||||
NvU32 gpcId;
|
||||
NvU32 tpcMask;
|
||||
} NV2080_CTRL_GPU_GET_FERMI_TPC_INFO_PARAMS;
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS {
|
||||
NvU32 gpcId;
|
||||
NvU32 zcullMask;
|
||||
} NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS;
|
||||
|
||||
#define NV2080_GPU_MAX_GID_LENGTH (0x000000100ULL)
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_GET_GID_INFO_PARAMS {
|
||||
NvU32 index;
|
||||
NvU32 flags;
|
||||
NvU32 length;
|
||||
NvU8 data[NV2080_GPU_MAX_GID_LENGTH];
|
||||
} NV2080_CTRL_GPU_GET_GID_INFO_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,41 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080gr_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080gr_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_MAIN = 0,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_SPILL = 1,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_PAGEPOOL = 2,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_BETACB = 3,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_RTV = 4,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL = 5,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL = 6,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_CONTEXT_POOL_CONTROL_CPU = 7,
|
||||
NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS_END = 8,
|
||||
} NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS;
|
||||
|
||||
#endif
|
||||
@@ -1,162 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
|
||||
NvU32 feHwSysCap;
|
||||
NvU32 windowPresentMask;
|
||||
NvBool bFbRemapperEnabled;
|
||||
NvU32 numHeads;
|
||||
NvBool bPrimaryVga;
|
||||
NvU32 i2cPort;
|
||||
NvU32 internalDispActiveMask;
|
||||
} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO {
|
||||
NvU32 size;
|
||||
NvU32 alignment;
|
||||
} NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO;
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
|
||||
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
|
||||
NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO {
|
||||
NvU32 engDesc;
|
||||
NvU32 ctxAttr;
|
||||
NvU32 ctxBufferSize;
|
||||
NvU32 addrSpaceList;
|
||||
NvU32 registerBase;
|
||||
} NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS 0x40
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
|
||||
NvU32 numConstructedFalcons;
|
||||
NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
|
||||
} NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 instMemSize, 8);
|
||||
NvU32 instMemAddrSpace;
|
||||
NvU32 instMemCpuCacheAttr;
|
||||
} NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
|
||||
NvU32 addressSpace;
|
||||
NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 limit, 8);
|
||||
NvU32 cacheSnoop;
|
||||
NvU32 hclass;
|
||||
NvU32 channelInstance;
|
||||
NvBool valid;
|
||||
} NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128
|
||||
|
||||
typedef enum NV2080_INTR_CATEGORY {
|
||||
NV2080_INTR_CATEGORY_DEFAULT = 0,
|
||||
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
|
||||
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
|
||||
NV2080_INTR_CATEGORY_RUNLIST = 3,
|
||||
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
|
||||
NV2080_INTR_CATEGORY_UVM_OWNED = 5,
|
||||
NV2080_INTR_CATEGORY_UVM_SHARED = 6,
|
||||
NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
|
||||
} NV2080_INTR_CATEGORY;
|
||||
|
||||
typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
|
||||
NvU8 subtreeStart;
|
||||
NvU8 subtreeEnd;
|
||||
} NV2080_INTR_CATEGORY_SUBTREE_MAP;
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
|
||||
NvU16 engineIdx;
|
||||
NvU32 pmcIntrMask;
|
||||
NvU32 vectorStall;
|
||||
NvU32 vectorNonStall;
|
||||
} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY;
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
|
||||
NvU32 tableLen;
|
||||
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
|
||||
NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
|
||||
} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
|
||||
NvU32 fbsrType;
|
||||
NvU32 numRegions;
|
||||
NvHandle hClient;
|
||||
NvHandle hSysMem;
|
||||
NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
|
||||
NvBool bEnteringGcoffState;
|
||||
} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS {
|
||||
NvU32 fbsrType;
|
||||
NvHandle hClient;
|
||||
NvHandle hVidMem;
|
||||
NV_DECLARE_ALIGNED(NvU64 vidOffset, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 sysOffset, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 size, 8);
|
||||
} NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_ACPI_DSM_READ_SIZE (0x1000) /* finn: Evaluated from "(4 * 1024)" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS {
|
||||
NvU32 status;
|
||||
NvU16 backLightDataSize;
|
||||
NvU8 backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE];
|
||||
} NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,95 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define GMMU_FMT_MAX_LEVELS 6U
|
||||
|
||||
#define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
|
||||
/*!
|
||||
* [in] GPU sub-device handle - this API only supports unicast.
|
||||
* Pass 0 to use subDeviceId instead.
|
||||
*/
|
||||
NvHandle hSubDevice;
|
||||
|
||||
/*!
|
||||
* [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
|
||||
*/
|
||||
NvU32 subDeviceId;
|
||||
|
||||
/*!
|
||||
* [in] Page size (VA coverage) of the level to reserve.
|
||||
* This need not be a leaf (page table) page size - it can be
|
||||
* the coverage of an arbitrary level (including root page directory).
|
||||
*/
|
||||
NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
|
||||
|
||||
/*!
|
||||
* [in] First GPU virtual address of the range to reserve.
|
||||
* This must be aligned to pageSize.
|
||||
*/
|
||||
NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
|
||||
|
||||
/*!
|
||||
* [in] Last GPU virtual address of the range to reserve.
|
||||
* This (+1) must be aligned to pageSize.
|
||||
*/
|
||||
NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
|
||||
|
||||
/*!
|
||||
* [in] Number of PDE levels to copy.
|
||||
*/
|
||||
NvU32 numLevelsToCopy;
|
||||
|
||||
/*!
|
||||
* [in] Per-level information.
|
||||
*/
|
||||
struct {
|
||||
/*!
|
||||
* Physical address of this page level instance.
|
||||
*/
|
||||
NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
|
||||
|
||||
/*!
|
||||
* Size in bytes allocated for this level instance.
|
||||
*/
|
||||
NV_DECLARE_ALIGNED(NvU64 size, 8);
|
||||
|
||||
/*!
|
||||
* Aperture in which this page level instance resides.
|
||||
*/
|
||||
NvU32 aperture;
|
||||
|
||||
/*!
|
||||
* Page shift corresponding to the level
|
||||
*/
|
||||
NvU8 pageShift;
|
||||
} levels[GMMU_FMT_MAX_LEVELS];
|
||||
} NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,42 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_ctrl_ctrla06f_ctrla06fgpfifo_h__
|
||||
#define __src_common_sdk_nvidia_inc_ctrl_ctrla06f_ctrla06fgpfifo_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NVA06F_CTRL_CMD_GPFIFO_SCHEDULE (0xa06f0103) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS {
|
||||
NvBool bEnable;
|
||||
NvBool bSkipSubmit;
|
||||
} NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS;
|
||||
|
||||
#define NVA06F_CTRL_CMD_BIND (0xa06f0104) /* finn: Evaluated from "(FINN_KEPLER_CHANNEL_GPFIFO_A_GPFIFO_INTERFACE_ID << 8) | NVA06F_CTRL_BIND_PARAMS_MESSAGE_ID" */
|
||||
|
||||
typedef struct NVA06F_CTRL_BIND_PARAMS {
|
||||
NvU32 engineType;
|
||||
} NVA06F_CTRL_BIND_PARAMS;
|
||||
|
||||
#endif
|
||||
@@ -1,33 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_nvlimits_h__
|
||||
#define __src_common_sdk_nvidia_inc_nvlimits_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV_MAX_SUBDEVICES 8
|
||||
|
||||
#define NV_PROC_NAME_MAX_LENGTH 100U
|
||||
|
||||
#endif
|
||||
@@ -1,148 +0,0 @@
|
||||
#ifndef __src_common_sdk_nvidia_inc_nvos_h__
|
||||
#define __src_common_sdk_nvidia_inc_nvos_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NVOS02_FLAGS_PHYSICALITY 7:4
|
||||
#define NVOS02_FLAGS_PHYSICALITY_CONTIGUOUS (0x00000000)
|
||||
#define NVOS02_FLAGS_PHYSICALITY_NONCONTIGUOUS (0x00000001)
|
||||
#define NVOS02_FLAGS_LOCATION 11:8
|
||||
#define NVOS02_FLAGS_LOCATION_PCI (0x00000000)
|
||||
#define NVOS02_FLAGS_LOCATION_AGP (0x00000001)
|
||||
#define NVOS02_FLAGS_LOCATION_VIDMEM (0x00000002)
|
||||
#define NVOS02_FLAGS_COHERENCY 15:12
|
||||
#define NVOS02_FLAGS_COHERENCY_UNCACHED (0x00000000)
|
||||
#define NVOS02_FLAGS_COHERENCY_CACHED (0x00000001)
|
||||
#define NVOS02_FLAGS_COHERENCY_WRITE_COMBINE (0x00000002)
|
||||
#define NVOS02_FLAGS_COHERENCY_WRITE_THROUGH (0x00000003)
|
||||
#define NVOS02_FLAGS_COHERENCY_WRITE_PROTECT (0x00000004)
|
||||
#define NVOS02_FLAGS_COHERENCY_WRITE_BACK (0x00000005)
|
||||
#define NVOS02_FLAGS_ALLOC 17:16
|
||||
#define NVOS02_FLAGS_ALLOC_NONE (0x00000001)
|
||||
#define NVOS02_FLAGS_GPU_CACHEABLE 18:18
|
||||
#define NVOS02_FLAGS_GPU_CACHEABLE_NO (0x00000000)
|
||||
#define NVOS02_FLAGS_GPU_CACHEABLE_YES (0x00000001)
|
||||
|
||||
#define NVOS02_FLAGS_KERNEL_MAPPING 19:19
|
||||
#define NVOS02_FLAGS_KERNEL_MAPPING_NO_MAP (0x00000000)
|
||||
#define NVOS02_FLAGS_KERNEL_MAPPING_MAP (0x00000001)
|
||||
#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY 20:20
|
||||
#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_NO (0x00000000)
|
||||
#define NVOS02_FLAGS_ALLOC_NISO_DISPLAY_YES (0x00000001)
|
||||
|
||||
#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY 21:21
|
||||
#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_NO (0x00000000)
|
||||
#define NVOS02_FLAGS_ALLOC_USER_READ_ONLY_YES (0x00000001)
|
||||
|
||||
#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY 22:22
|
||||
#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_NO (0x00000000)
|
||||
#define NVOS02_FLAGS_ALLOC_DEVICE_READ_ONLY_YES (0x00000001)
|
||||
|
||||
#define NVOS02_FLAGS_PEER_MAP_OVERRIDE 23:23
|
||||
#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_DEFAULT (0x00000000)
|
||||
#define NVOS02_FLAGS_PEER_MAP_OVERRIDE_REQUIRED (0x00000001)
|
||||
|
||||
#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT 24:24
|
||||
#define NVOS02_FLAGS_ALLOC_TYPE_SYNCPOINT_APERTURE (0x00000001)
|
||||
|
||||
#define NVOS02_FLAGS_MEMORY_PROTECTION 26:25
|
||||
#define NVOS02_FLAGS_MEMORY_PROTECTION_DEFAULT (0x00000000)
|
||||
#define NVOS02_FLAGS_MEMORY_PROTECTION_PROTECTED (0x00000001)
|
||||
#define NVOS02_FLAGS_MEMORY_PROTECTION_UNPROTECTED (0x00000002)
|
||||
|
||||
#define NVOS02_FLAGS_MAPPING 31:30
|
||||
#define NVOS02_FLAGS_MAPPING_DEFAULT (0x00000000)
|
||||
#define NVOS02_FLAGS_MAPPING_NO_MAP (0x00000001)
|
||||
#define NVOS02_FLAGS_MAPPING_NEVER_MAP (0x00000002)
|
||||
|
||||
#define NV01_EVENT_CLIENT_RM (0x04000000)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvV32 channelInstance; // One of the n channel instances of a given channel type.
|
||||
// Note that core channel has only one instance
|
||||
// while all others have two (one per head).
|
||||
NvHandle hObjectBuffer; // ctx dma handle for DMA push buffer
|
||||
NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors/notifications
|
||||
NvU32 offset; // Initial offset for put/get, usually zero.
|
||||
NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of UDISP GET/PUT regs
|
||||
|
||||
NvU32 flags;
|
||||
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB 1:1
|
||||
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_YES 0x00000000
|
||||
#define NV50VAIO_CHANNELDMA_ALLOCATION_FLAGS_CONNECT_PB_AT_GRAB_NO 0x00000001
|
||||
|
||||
} NV50VAIO_CHANNELDMA_ALLOCATION_PARAMETERS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvV32 channelInstance; // One of the n channel instances of a given channel type.
|
||||
// All PIO channels have two instances (one per head).
|
||||
NvHandle hObjectNotify; // ctx dma handle for an area (of type NvNotification defined in sdk/nvidia/inc/nvtypes.h) where RM can write errors.
|
||||
NvP64 pControl NV_ALIGN_BYTES(8); // pControl gives virt addr of control region for PIO channel
|
||||
} NV50VAIO_CHANNELPIO_ALLOCATION_PARAMETERS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 size;
|
||||
NvU32 prohibitMultipleInstances;
|
||||
NvU32 engineInstance; // Select NVDEC0 or NVDEC1 or NVDEC2
|
||||
} NV_BSP_ALLOCATION_PARAMETERS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 size;
|
||||
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC?
|
||||
NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2
|
||||
} NV_MSENC_ALLOCATION_PARAMETERS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 size;
|
||||
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of NVJPG?
|
||||
NvU32 engineInstance;
|
||||
} NV_NVJPG_ALLOCATION_PARAMETERS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 size;
|
||||
NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of OFA?
|
||||
} NV_OFA_ALLOCATION_PARAMETERS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 index;
|
||||
NvV32 flags;
|
||||
NvU64 vaSize NV_ALIGN_BYTES(8);
|
||||
NvU64 vaStartInternal NV_ALIGN_BYTES(8);
|
||||
NvU64 vaLimitInternal NV_ALIGN_BYTES(8);
|
||||
NvU32 bigPageSize;
|
||||
NvU64 vaBase NV_ALIGN_BYTES(8);
|
||||
} NV_VASPACE_ALLOCATION_PARAMETERS;
|
||||
|
||||
#define NV_VASPACE_ALLOCATION_INDEX_GPU_NEW 0x00 //<! Create new VASpace, by default
|
||||
|
||||
#endif
|
||||
@@ -1,97 +0,0 @@
|
||||
#ifndef __src_common_shared_msgq_inc_msgq_msgq_priv_h__
|
||||
#define __src_common_shared_msgq_inc_msgq_msgq_priv_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* msgqTxHeader -- TX queue data structure
|
||||
* @version: the version of this structure, must be 0
|
||||
* @size: the size of the entire queue, including this header
|
||||
* @msgSize: the padded size of queue element, 16 is minimum
|
||||
* @msgCount: the number of elements in this queue
|
||||
* @writePtr: head index of this queue
|
||||
* @flags: 1 = swap the RX pointers
|
||||
* @rxHdrOff: offset of readPtr in this structure
|
||||
* @entryOff: offset of beginning of queue (msgqRxHeader), relative to
|
||||
* beginning of this structure
|
||||
*
|
||||
* The command queue is a queue of RPCs that are sent from the driver to the
|
||||
* GSP. The status queue is a queue of messages/responses from GSP-RM to the
|
||||
* driver. Although the driver allocates memory for both queues, the command
|
||||
* queue is owned by the driver and the status queue is owned by GSP-RM. In
|
||||
* addition, the headers of the two queues must not share the same 4K page.
|
||||
*
|
||||
* Each queue is prefixed with this data structure. The idea is that a queue
|
||||
* and its header are written to only by their owner. That is, only the
|
||||
* driver writes to the command queue and command queue header, and only the
|
||||
* GSP writes to the status (receive) queue and its header.
|
||||
*
|
||||
* This is enforced by the concept of "swapping" the RX pointers. This is
|
||||
* why the 'flags' field must be set to 1. 'rxHdrOff' is how the GSP knows
|
||||
* where the where the tail pointer of its status queue.
|
||||
*
|
||||
* When the driver writes a new RPC to the command queue, it updates writePtr.
|
||||
* When it reads a new message from the status queue, it updates readPtr. In
|
||||
* this way, the GSP knows when a new command is in the queue (it polls
|
||||
* writePtr) and it knows how much free space is in the status queue (it
|
||||
* checks readPtr). The driver never cares about how much free space is in
|
||||
* the status queue.
|
||||
*
|
||||
* As usual, producers write to the head pointer, and consumers read from the
|
||||
* tail pointer. When head == tail, the queue is empty.
|
||||
*
|
||||
* So to summarize:
|
||||
* command.writePtr = head of command queue
|
||||
* command.readPtr = tail of status queue
|
||||
* status.writePtr = head of status queue
|
||||
* status.readPtr = tail of command queue
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
NvU32 version; // queue version
|
||||
NvU32 size; // bytes, page aligned
|
||||
NvU32 msgSize; // entry size, bytes, must be power-of-2, 16 is minimum
|
||||
NvU32 msgCount; // number of entries in queue
|
||||
NvU32 writePtr; // message id of next slot
|
||||
NvU32 flags; // if set it means "i want to swap RX"
|
||||
NvU32 rxHdrOff; // Offset of msgqRxHeader from start of backing store.
|
||||
NvU32 entryOff; // Offset of entries from start of backing store.
|
||||
} msgqTxHeader;
|
||||
|
||||
/**
|
||||
* msgqRxHeader - RX queue data structure
|
||||
* @readPtr: tail index of the other queue
|
||||
*
|
||||
* Although this is a separate struct, it could easily be merged into
|
||||
* msgqTxHeader. msgqTxHeader.rxHdrOff is simply the offset of readPtr
|
||||
* from the beginning of msgqTxHeader.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
NvU32 readPtr; // message id of last message read
|
||||
} msgqRxHeader;
|
||||
|
||||
#endif
|
||||
@@ -1,52 +0,0 @@
|
||||
#ifndef __src_common_uproc_os_common_include_libos_init_args_h__
|
||||
#define __src_common_uproc_os_common_include_libos_init_args_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef NvU64 LibosAddress;
|
||||
|
||||
typedef enum {
|
||||
LIBOS_MEMORY_REGION_NONE,
|
||||
LIBOS_MEMORY_REGION_CONTIGUOUS,
|
||||
LIBOS_MEMORY_REGION_RADIX3
|
||||
} LibosMemoryRegionKind;
|
||||
|
||||
typedef enum {
|
||||
LIBOS_MEMORY_REGION_LOC_NONE,
|
||||
LIBOS_MEMORY_REGION_LOC_SYSMEM,
|
||||
LIBOS_MEMORY_REGION_LOC_FB
|
||||
} LibosMemoryRegionLoc;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
LibosAddress id8; // Id tag.
|
||||
LibosAddress pa; // Physical address.
|
||||
LibosAddress size; // Size of memory area.
|
||||
NvU8 kind; // See LibosMemoryRegionKind above.
|
||||
NvU8 loc; // See LibosMemoryRegionLoc above.
|
||||
} LibosMemoryRegionInitArgument;
|
||||
|
||||
#endif
|
||||
@@ -1,79 +0,0 @@
|
||||
#ifndef __src_nvidia_arch_nvalloc_common_inc_gsp_gsp_fw_sr_meta_h__
|
||||
#define __src_nvidia_arch_nvalloc_common_inc_gsp_gsp_fw_sr_meta_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define GSP_FW_SR_META_MAGIC 0x8a3bb9e6c6c39d93ULL
|
||||
#define GSP_FW_SR_META_REVISION 2
|
||||
|
||||
typedef struct
|
||||
{
|
||||
//
|
||||
// Magic
|
||||
// Use for verification by Booter
|
||||
//
|
||||
NvU64 magic; // = GSP_FW_SR_META_MAGIC;
|
||||
|
||||
//
|
||||
// Revision number
|
||||
// Bumped up when we change this interface so it is not backward compatible.
|
||||
// Bumped up when we revoke GSP-RM ucode
|
||||
//
|
||||
NvU64 revision; // = GSP_FW_SR_META_MAGIC_REVISION;
|
||||
|
||||
//
|
||||
// ---- Members regarding data in SYSMEM ----------------------------
|
||||
// Consumed by Booter for DMA
|
||||
//
|
||||
NvU64 sysmemAddrOfSuspendResumeData;
|
||||
NvU64 sizeOfSuspendResumeData;
|
||||
|
||||
// ---- Members for crypto ops across S/R ---------------------------
|
||||
|
||||
//
|
||||
// HMAC over the entire GspFwSRMeta structure (including padding)
|
||||
// with the hmac field itself zeroed.
|
||||
//
|
||||
NvU8 hmac[32];
|
||||
|
||||
// Hash over GspFwWprMeta structure
|
||||
NvU8 wprMetaHash[32];
|
||||
|
||||
// Hash over GspFwHeapFreeList structure. All zeros signifies no free list.
|
||||
NvU8 heapFreeListHash[32];
|
||||
|
||||
// Hash over data in WPR2 (skipping over free heap chunks; see Booter for details)
|
||||
NvU8 dataHash[32];
|
||||
|
||||
//
|
||||
// Pad structure to exactly 256 bytes (1 DMA chunk).
|
||||
// Padding initialized to zero.
|
||||
//
|
||||
NvU32 padding[24];
|
||||
|
||||
} GspFwSRMeta;
|
||||
|
||||
#endif
|
||||
@@ -1,170 +0,0 @@
|
||||
#ifndef __src_nvidia_arch_nvalloc_common_inc_gsp_gsp_fw_wpr_meta_h__
|
||||
#define __src_nvidia_arch_nvalloc_common_inc_gsp_gsp_fw_wpr_meta_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
// Magic
|
||||
// BL to use for verification (i.e. Booter locked it in WPR2)
|
||||
NvU64 magic; // = 0xdc3aae21371a60b3;
|
||||
|
||||
// Revision number of Booter-BL-Sequencer handoff interface
|
||||
// Bumped up when we change this interface so it is not backward compatible.
|
||||
// Bumped up when we revoke GSP-RM ucode
|
||||
NvU64 revision; // = 1;
|
||||
|
||||
// ---- Members regarding data in SYSMEM ----------------------------
|
||||
// Consumed by Booter for DMA
|
||||
|
||||
NvU64 sysmemAddrOfRadix3Elf;
|
||||
NvU64 sizeOfRadix3Elf;
|
||||
|
||||
NvU64 sysmemAddrOfBootloader;
|
||||
NvU64 sizeOfBootloader;
|
||||
|
||||
// Offsets inside bootloader image needed by Booter
|
||||
NvU64 bootloaderCodeOffset;
|
||||
NvU64 bootloaderDataOffset;
|
||||
NvU64 bootloaderManifestOffset;
|
||||
|
||||
union
|
||||
{
|
||||
// Used only at initial boot
|
||||
struct
|
||||
{
|
||||
NvU64 sysmemAddrOfSignature;
|
||||
NvU64 sizeOfSignature;
|
||||
};
|
||||
|
||||
//
|
||||
// Used at suspend/resume to read GspFwHeapFreeList
|
||||
// Offset relative to GspFwWprMeta FBMEM PA (gspFwWprStart)
|
||||
//
|
||||
struct
|
||||
{
|
||||
NvU32 gspFwHeapFreeListWprOffset;
|
||||
NvU32 unused0;
|
||||
NvU64 unused1;
|
||||
};
|
||||
};
|
||||
|
||||
// ---- Members describing FB layout --------------------------------
|
||||
NvU64 gspFwRsvdStart;
|
||||
|
||||
NvU64 nonWprHeapOffset;
|
||||
NvU64 nonWprHeapSize;
|
||||
|
||||
NvU64 gspFwWprStart;
|
||||
|
||||
// GSP-RM to use to setup heap.
|
||||
NvU64 gspFwHeapOffset;
|
||||
NvU64 gspFwHeapSize;
|
||||
|
||||
// BL to use to find ELF for jump
|
||||
NvU64 gspFwOffset;
|
||||
// Size is sizeOfRadix3Elf above.
|
||||
|
||||
NvU64 bootBinOffset;
|
||||
// Size is sizeOfBootloader above.
|
||||
|
||||
NvU64 frtsOffset;
|
||||
NvU64 frtsSize;
|
||||
|
||||
NvU64 gspFwWprEnd;
|
||||
|
||||
// GSP-RM to use for fbRegionInfo?
|
||||
NvU64 fbSize;
|
||||
|
||||
// ---- Other members -----------------------------------------------
|
||||
|
||||
// GSP-RM to use for fbRegionInfo?
|
||||
NvU64 vgaWorkspaceOffset;
|
||||
NvU64 vgaWorkspaceSize;
|
||||
|
||||
// Boot count. Used to determine whether to load the firmware image.
|
||||
NvU64 bootCount;
|
||||
|
||||
// TODO: the partitionRpc* fields below do not really belong in this
|
||||
// structure. The values are patched in by the partition bootstrapper
|
||||
// when GSP-RM is booted in a partition, and this structure was a
|
||||
// convenient place for the bootstrapper to access them. These should
|
||||
// be moved to a different comm. mechanism between the bootstrapper
|
||||
// and the GSP-RM tasks.
|
||||
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
// Shared partition RPC memory (physical address)
|
||||
NvU64 partitionRpcAddr;
|
||||
|
||||
// Offsets relative to partitionRpcAddr
|
||||
NvU16 partitionRpcRequestOffset;
|
||||
NvU16 partitionRpcReplyOffset;
|
||||
|
||||
// Code section and dataSection offset and size.
|
||||
NvU32 elfCodeOffset;
|
||||
NvU32 elfDataOffset;
|
||||
NvU32 elfCodeSize;
|
||||
NvU32 elfDataSize;
|
||||
|
||||
// Used during GSP-RM resume to check for revocation
|
||||
NvU32 lsUcodeVersion;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
// Pad for the partitionRpc* fields, plus 4 bytes
|
||||
NvU32 partitionRpcPadding[4];
|
||||
|
||||
// CrashCat (contiguous) buffer size/location - occupies same bytes as the
|
||||
// elf(Code|Data)(Offset|Size) fields above.
|
||||
// TODO: move to GSP_FMC_INIT_PARAMS
|
||||
NvU64 sysmemAddrOfCrashReportQueue;
|
||||
NvU32 sizeOfCrashReportQueue;
|
||||
|
||||
// Pad for the lsUcodeVersion field
|
||||
NvU32 lsUcodeVersionPadding[1];
|
||||
};
|
||||
};
|
||||
|
||||
// Number of VF partitions allocating sub-heaps from the WPR heap
|
||||
// Used during boot to ensure the heap is adequately sized
|
||||
NvU8 gspFwHeapVfPartitionCount;
|
||||
|
||||
// Pad structure to exactly 256 bytes. Can replace padding with additional
|
||||
// fields without incrementing revision. Padding initialized to 0.
|
||||
NvU8 padding[7];
|
||||
|
||||
// BL to use for verification (i.e. Booter says OK to boot)
|
||||
NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified
|
||||
} GspFwWprMeta;
|
||||
|
||||
#define GSP_FW_WPR_META_REVISION 1
|
||||
#define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL
|
||||
|
||||
#endif
|
||||
@@ -1,82 +0,0 @@
|
||||
#ifndef __src_nvidia_arch_nvalloc_common_inc_rmRiscvUcode_h__
|
||||
#define __src_nvidia_arch_nvalloc_common_inc_rmRiscvUcode_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
//
|
||||
// Version 1
|
||||
// Version 2
|
||||
// Version 3 = for Partition boot
|
||||
// Version 4 = for eb riscv boot
|
||||
// Version 5 = Support signing entire RISC-V image as "code" in code section for hopper and later.
|
||||
//
|
||||
NvU32 version; // structure version
|
||||
NvU32 bootloaderOffset;
|
||||
NvU32 bootloaderSize;
|
||||
NvU32 bootloaderParamOffset;
|
||||
NvU32 bootloaderParamSize;
|
||||
NvU32 riscvElfOffset;
|
||||
NvU32 riscvElfSize;
|
||||
NvU32 appVersion; // Changelist number associated with the image
|
||||
//
|
||||
// Manifest contains information about Monitor and it is
|
||||
// input to BR
|
||||
//
|
||||
NvU32 manifestOffset;
|
||||
NvU32 manifestSize;
|
||||
//
|
||||
// Monitor Data offset within RISCV image and size
|
||||
//
|
||||
NvU32 monitorDataOffset;
|
||||
NvU32 monitorDataSize;
|
||||
//
|
||||
// Monitor Code offset withtin RISCV image and size
|
||||
//
|
||||
NvU32 monitorCodeOffset;
|
||||
NvU32 monitorCodeSize;
|
||||
NvU32 bIsMonitorEnabled;
|
||||
//
|
||||
// Swbrom Code offset within RISCV image and size
|
||||
//
|
||||
NvU32 swbromCodeOffset;
|
||||
NvU32 swbromCodeSize;
|
||||
//
|
||||
// Swbrom Data offset within RISCV image and size
|
||||
//
|
||||
NvU32 swbromDataOffset;
|
||||
NvU32 swbromDataSize;
|
||||
//
|
||||
// Total size of FB carveout (image and reserved space).
|
||||
//
|
||||
NvU32 fbReservedSize;
|
||||
//
|
||||
// Indicates whether the entire RISC-V image is signed as "code" in code section.
|
||||
//
|
||||
NvU32 bSignedAsCode;
|
||||
} RM_RISCV_UCODE_DESC;
|
||||
|
||||
#endif
|
||||
@@ -1,100 +0,0 @@
|
||||
#ifndef __src_nvidia_arch_nvalloc_common_inc_rmgspseq_h__
|
||||
#define __src_nvidia_arch_nvalloc_common_inc_rmgspseq_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef enum GSP_SEQ_BUF_OPCODE
|
||||
{
|
||||
GSP_SEQ_BUF_OPCODE_REG_WRITE = 0,
|
||||
GSP_SEQ_BUF_OPCODE_REG_MODIFY,
|
||||
GSP_SEQ_BUF_OPCODE_REG_POLL,
|
||||
GSP_SEQ_BUF_OPCODE_DELAY_US,
|
||||
GSP_SEQ_BUF_OPCODE_REG_STORE,
|
||||
GSP_SEQ_BUF_OPCODE_CORE_RESET,
|
||||
GSP_SEQ_BUF_OPCODE_CORE_START,
|
||||
GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT,
|
||||
GSP_SEQ_BUF_OPCODE_CORE_RESUME,
|
||||
} GSP_SEQ_BUF_OPCODE;
|
||||
|
||||
#define GSP_SEQUENCER_PAYLOAD_SIZE_DWORDS(opcode) \
|
||||
((opcode == GSP_SEQ_BUF_OPCODE_REG_WRITE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_WRITE) / sizeof(NvU32)) : \
|
||||
(opcode == GSP_SEQ_BUF_OPCODE_REG_MODIFY) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_MODIFY) / sizeof(NvU32)) : \
|
||||
(opcode == GSP_SEQ_BUF_OPCODE_REG_POLL) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_POLL) / sizeof(NvU32)) : \
|
||||
(opcode == GSP_SEQ_BUF_OPCODE_DELAY_US) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_DELAY_US) / sizeof(NvU32)) : \
|
||||
(opcode == GSP_SEQ_BUF_OPCODE_REG_STORE) ? (sizeof(GSP_SEQ_BUF_PAYLOAD_REG_STORE) / sizeof(NvU32)) : \
|
||||
/* GSP_SEQ_BUF_OPCODE_CORE_RESET */ \
|
||||
/* GSP_SEQ_BUF_OPCODE_CORE_START */ \
|
||||
/* GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT */ \
|
||||
/* GSP_SEQ_BUF_OPCODE_CORE_RESUME */ \
|
||||
0)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 addr;
|
||||
NvU32 val;
|
||||
} GSP_SEQ_BUF_PAYLOAD_REG_WRITE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 addr;
|
||||
NvU32 mask;
|
||||
NvU32 val;
|
||||
} GSP_SEQ_BUF_PAYLOAD_REG_MODIFY;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 addr;
|
||||
NvU32 mask;
|
||||
NvU32 val;
|
||||
NvU32 timeout;
|
||||
NvU32 error;
|
||||
} GSP_SEQ_BUF_PAYLOAD_REG_POLL;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 val;
|
||||
} GSP_SEQ_BUF_PAYLOAD_DELAY_US;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 addr;
|
||||
NvU32 index;
|
||||
} GSP_SEQ_BUF_PAYLOAD_REG_STORE;
|
||||
|
||||
typedef struct GSP_SEQUENCER_BUFFER_CMD
|
||||
{
|
||||
GSP_SEQ_BUF_OPCODE opCode;
|
||||
union
|
||||
{
|
||||
GSP_SEQ_BUF_PAYLOAD_REG_WRITE regWrite;
|
||||
GSP_SEQ_BUF_PAYLOAD_REG_MODIFY regModify;
|
||||
GSP_SEQ_BUF_PAYLOAD_REG_POLL regPoll;
|
||||
GSP_SEQ_BUF_PAYLOAD_DELAY_US delayUs;
|
||||
GSP_SEQ_BUF_PAYLOAD_REG_STORE regStore;
|
||||
} payload;
|
||||
} GSP_SEQUENCER_BUFFER_CMD;
|
||||
|
||||
#endif
|
||||
@@ -1,33 +0,0 @@
|
||||
#ifndef __src_nvidia_generated_g_allclasses_h__
|
||||
#define __src_nvidia_generated_g_allclasses_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define NV01_EVENT_KERNEL_CALLBACK_EX (0x0000007e)
|
||||
|
||||
#define NV04_DISPLAY_COMMON (0x00000073)
|
||||
|
||||
#endif
|
||||
@@ -1,38 +0,0 @@
|
||||
#ifndef __src_nvidia_generated_g_chipset_nvoc_h__
|
||||
#define __src_nvidia_generated_g_chipset_nvoc_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU16 deviceID; // deviceID
|
||||
NvU16 vendorID; // vendorID
|
||||
NvU16 subdeviceID; // subsystem deviceID
|
||||
NvU16 subvendorID; // subsystem vendorID
|
||||
NvU8 revisionID; // revision ID
|
||||
} BUSINFO;
|
||||
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
#ifndef __src_nvidia_generated_g_fbsr_nvoc_h__
|
||||
#define __src_nvidia_generated_g_fbsr_nvoc_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2009-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#define FBSR_TYPE_DMA 4 // Copy using DMA. Fastest.
|
||||
|
||||
#endif
|
||||
@@ -1,35 +0,0 @@
|
||||
#ifndef __src_nvidia_generated_g_gpu_nvoc_h__
|
||||
#define __src_nvidia_generated_g_gpu_nvoc_h__
|
||||
|
||||
/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
COMPUTE_BRANDING_TYPE_NONE,
|
||||
COMPUTE_BRANDING_TYPE_TESLA,
|
||||
} COMPUTE_BRANDING_TYPE;
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user