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drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer

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The stage contains configuration for a mixer pair. Currently the plane
supports just one stage and 2 pipes. Quad-pipe support will require
handling 2 stages and 4 pipes at the same time. In preparation for that
add a separate define, PIPES_PER_PLANE, to denote number of pipes that
can be used by the plane.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/675408/
Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-5-ff6232e3472f@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Jun Nie
2025-09-18 21:28:57 +08:00
committed by Dmitry Baryshkov
parent fb4c972b63
commit 5d45171e26
4 changed files with 15 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
View File

@@ -472,8 +472,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
for (i = 0; i < PIPES_PER_STAGE; i++) {
for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!pstate->pipe[i].sspp)
continue;
set_bit(pstate->pipe[i].sspp->idx, active_fetch);
@@ -1305,7 +1304,7 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state
return ret;
}
#define MAX_CHANNELS_PER_CRTC 2
#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE
#define MAX_HDISPLAY_SPLIT 1080
static struct msm_display_topology dpu_crtc_get_topology(
@@ -1678,7 +1677,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
state->crtc_x, state->crtc_y, state->crtc_w,
state->crtc_h);
for (i = 0; i < PIPES_PER_STAGE; i++) {
for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!pstate->pipe[i].sspp)
continue;
seq_printf(s, "\tsspp[%d]:%s\n",

1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
View File

@@ -34,6 +34,7 @@
#define DPU_MAX_PLANES 4
#endif
#define PIPES_PER_PLANE 2
#define PIPES_PER_STAGE 2
#ifndef DPU_MAX_DE_CURVES
#define DPU_MAX_DE_CURVES 3

19
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View File

@@ -636,7 +636,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
return;
/* update sspp */
for (i = 0; i < PIPES_PER_STAGE; i++) {
for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!pstate->pipe[i].sspp)
continue;
_dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i],
@@ -1159,7 +1159,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
* resources are freed by dpu_crtc_assign_plane_resources(),
* but clean them here.
*/
for (i = 0; i < PIPES_PER_STAGE; i++)
for (i = 0; i < PIPES_PER_PLANE; i++)
pstate->pipe[i].sspp = NULL;
return 0;
@@ -1213,7 +1213,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
pipe_cfg = &pstate->pipe_cfg[0];
r_pipe_cfg = &pstate->pipe_cfg[1];
for (i = 0; i < PIPES_PER_STAGE; i++)
for (i = 0; i < PIPES_PER_PLANE; i++)
pstate->pipe[i].sspp = NULL;
if (!plane_state->fb)
@@ -1346,7 +1346,7 @@ void dpu_plane_flush(struct drm_plane *plane)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
else {
for (i = 0; i < PIPES_PER_STAGE; i++)
for (i = 0; i < PIPES_PER_PLANE; i++)
dpu_plane_flush_csc(pdpu, &pstate->pipe[i]);
}
@@ -1468,8 +1468,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
crtc->base.id, DRM_RECT_ARG(&state->dst),
&fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
/* move the assignment here, to ease handling to another pairs later */
for (i = 0; i < PIPES_PER_STAGE; i++) {
for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect))
continue;
dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i],
@@ -1483,7 +1482,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
pstate->plane_fetch_bw = 0;
pstate->plane_clk = 0;
for (i = 0; i < PIPES_PER_STAGE; i++) {
for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!drm_rect_width(&pstate->pipe_cfg[i].src_rect))
continue;
pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt,
@@ -1502,7 +1501,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane)
struct dpu_sw_pipe *pipe;
int i;
for (i = 0; i < PIPES_PER_STAGE; i += 1) {
for (i = 0; i < PIPES_PER_PLANE; i += 1) {
pipe = &pstate->pipe[i];
if (!pipe->sspp)
continue;
@@ -1621,7 +1620,7 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
drm_printf(p, "\tstage=%d\n", pstate->stage);
for (i = 0; i < PIPES_PER_STAGE; i++) {
for (i = 0; i < PIPES_PER_PLANE; i++) {
pipe = &pstate->pipe[i];
if (!pipe->sspp)
continue;
@@ -1678,7 +1677,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
return;
pm_runtime_get_sync(&dpu_kms->pdev->dev);
for (i = 0; i < PIPES_PER_STAGE; i++) {
for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!pstate->pipe[i].sspp)
continue;
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable);

4
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
View File

@@ -31,8 +31,8 @@
*/
struct dpu_plane_state {
struct drm_plane_state base;
struct dpu_sw_pipe pipe[PIPES_PER_STAGE];
struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE];
struct dpu_sw_pipe pipe[PIPES_PER_PLANE];
struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE];
enum dpu_stage stage;
bool needs_qos_remap;
bool pending;