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drm/amd/powerplay/polaris10: mark symbols static where possible

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We get a few warnings when building kernel with W=1:
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/polaris10_clockpowergating.c:34:5: warning: no previous prototype
for 'polaris10_phm_powerup_uvd' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/polaris10_thermal.c:428:5: warning: no previous prototype
for 'tf_polaris10_thermal_setup_fan_table' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/polaris10_hwmgr.c:125:31: warning: no previous prototype
for 'cast_phw_polaris10_power_state' [-Wmissing-prototypes]
....

In fact, these functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Baoyou Xie
2016-09-06 15:17:48 +08:00
committed by Alex Deucher
parent 812a4654bb
commit 5cd92f86f0
3 changed files with 44 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
View File

@@ -31,7 +31,7 @@ int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
static int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_uvd_power_gating(hwmgr)) {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -47,7 +47,7 @@ int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
static int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -55,7 +55,7 @@ int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr)
static int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -63,7 +63,7 @@ int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
static int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))
@@ -72,7 +72,7 @@ int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr)
static int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))

63
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
View File

@@ -109,7 +109,7 @@ enum DPM_EVENT_SRC {
static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
struct polaris10_power_state *cast_phw_polaris10_power_state(
static struct polaris10_power_state *cast_phw_polaris10_power_state(
struct pp_hw_power_state *hw_ps)
{
PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
@@ -119,7 +119,8 @@ struct polaris10_power_state *cast_phw_polaris10_power_state(
return (struct polaris10_power_state *)hw_ps;
}
const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
static const struct polaris10_power_state *
cast_const_phw_polaris10_power_state(
const struct pp_hw_power_state *hw_ps)
{
PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
@@ -142,7 +143,7 @@ static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
static int phm_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
{
cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
@@ -151,7 +152,7 @@ int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
return 0;
}
uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
static uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
{
uint32_t speedCntl = 0;
@@ -162,7 +163,7 @@ uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
}
int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
static int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
{
uint32_t link_width;
@@ -182,7 +183,7 @@ int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
* @param pHwMgr the address of the powerplay hardware manager.
* @return always PP_Result_OK
*/
int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
static int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
{
PP_ASSERT_WITH_CODE(
(hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
@@ -662,7 +663,7 @@ static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
* on the power policy or external client requests,
* such as UVD request, etc.
*/
int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
static int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
@@ -836,7 +837,7 @@ static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
* @return always 0
*/
int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
struct SMU74_Discrete_DpmTable *table)
{
polaris10_populate_smc_vddci_table(hwmgr, table);
@@ -1413,7 +1414,7 @@ static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
* @param voltage the SMC VOLTAGE structure to be populated
*/
int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
uint32_t mclk, SMIO_Pattern *smio_pat)
{
const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
@@ -1927,7 +1928,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
}
int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
@@ -2556,7 +2557,7 @@ static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
}
int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
static int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
data->pcie_performance_request = true;
@@ -2564,7 +2565,7 @@ int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
static int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
@@ -2745,12 +2746,12 @@ int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
static int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
return phm_hwmgr_backend_fini(hwmgr);
}
int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
static int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
@@ -3105,7 +3106,7 @@ static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
static int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
{
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -3149,7 +3150,7 @@ int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
}
int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
static int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data;
struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
@@ -4359,7 +4360,8 @@ static int polaris10_generate_dpm_level_enable_mask(
return 0;
}
int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
static int
polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
PPSMC_MSG_UVDDPM_Enable :
@@ -4373,7 +4375,8 @@ int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
PPSMC_MSG_VCEDPM_Disable);
}
int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
static int
polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable?
PPSMC_MSG_SAMUDPM_Enable :
@@ -4687,14 +4690,16 @@ static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_
}
int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
static int
polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
{
PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
}
int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
static int
polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
{
uint32_t num_active_displays = 0;
struct cgs_display_info info = {0};
@@ -4717,7 +4722,7 @@ int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwm
* @param hwmgr the address of the powerplay hardware manager.
* @return always OK
*/
int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
static int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
uint32_t num_active_displays = 0;
@@ -4762,7 +4767,7 @@ int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
}
int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
static int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
{
return polaris10_program_display_gap(hwmgr);
}
@@ -4786,13 +4791,15 @@ static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_
PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
}
int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
static int
polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
const void *thermal_interrupt_info)
{
return 0;
}
bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
static bool polaris10_check_smc_update_required_for_display_configuration(
struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
bool is_update_required = false;
@@ -4822,7 +4829,9 @@ static inline bool polaris10_are_power_levels_equal(const struct polaris10_perfo
(pl1->pcie_lane == pl2->pcie_lane));
}
int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
static int polaris10_check_states_equal(struct pp_hwmgr *hwmgr,
const struct pp_hw_power_state *pstate1,
const struct pp_hw_power_state *pstate2, bool *equal)
{
const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
@@ -4853,7 +4862,7 @@ int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_powe
return 0;
}
int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
static int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
@@ -4966,7 +4975,7 @@ static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
static int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;

6
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
View File

@@ -152,7 +152,7 @@ int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
return 0;
}
int polaris10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
static int polaris10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
int result;
@@ -425,7 +425,7 @@ int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
static int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
@@ -537,7 +537,7 @@ int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
* @param Result the last failure code
* @return result from set temperature range routine
*/
int tf_polaris10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
static int tf_polaris10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr,
void *input, void *output, void *storage, int result)
{
/* If the fantable setup has failed we could have disabled