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synced 2026-08-30 14:33:24 -04:00
wifi: rtw89: unify access struct of TX power track tables
There are two struct to access TX power track tables. One is to access driver built-in tables, and the other one is to access the tables in fw element. As we are going to remove the built-in tables from driver, unify to use the struct as fw element style. The precedence is to use tables in fw element if present, and then built-in tables. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260707091056.42771-15-pkshih@realtek.com
This commit is contained in:
@@ -353,25 +353,6 @@ struct rtw89_txpwr_byrate_cfg {
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u32 data;
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};
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struct rtw89_txpwr_track_cfg {
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const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
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const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
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const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
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const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
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const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
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const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
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const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
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const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
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const s8 *delta_swingidx_2gb_n;
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const s8 *delta_swingidx_2gb_p;
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const s8 *delta_swingidx_2ga_n;
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const s8 *delta_swingidx_2ga_p;
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const s8 *delta_swingidx_2g_cck_b_n;
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const s8 *delta_swingidx_2g_cck_b_p;
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const s8 *delta_swingidx_2g_cck_a_n;
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const s8 *delta_swingidx_2g_cck_a_p;
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};
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struct rtw89_phy_dig_gain_cfg {
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const struct rtw89_reg_def *table;
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u8 size;
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@@ -2823,6 +2823,7 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
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} \
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__val; \
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})
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const struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
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struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
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u8 ch = chan->channel;
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u8 subband = chan->subband_type;
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@@ -2833,23 +2834,26 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
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u32 tmp = 0;
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u8 i, j;
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if (!trk)
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trk = &rtw89_8851b_trk_cfg;
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switch (subband) {
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default:
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case RTW89_CH_2G:
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thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_2ga_p;
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thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_2ga_n;
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
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break;
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case RTW89_CH_5G_BAND_1:
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thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[0];
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thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[0];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
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break;
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case RTW89_CH_5G_BAND_3:
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thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[1];
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thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[1];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
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break;
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case RTW89_CH_5G_BAND_4:
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thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[2];
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thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[2];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
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break;
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}
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@@ -2,6 +2,7 @@
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/* Copyright(c) 2022-2023 Realtek Corporation
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*/
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#include "fw.h"
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#include "phy.h"
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#include "reg.h"
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#include "rtw8851b_table.h"
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@@ -14866,13 +14867,13 @@ const struct rtw89_txpwr_table rtw89_8851b_byr_table_type2 = {
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.load = rtw89_phy_load_txpwr_byrate,
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};
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const struct rtw89_txpwr_track_cfg rtw89_8851b_trk_cfg = {
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.delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n,
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.delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p,
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.delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n,
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.delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p,
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.delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n,
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.delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
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const struct rtw89_fw_txpwr_track_cfg rtw89_8851b_trk_cfg = {
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.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N] = _txpwr_track_delta_swingidx_5ga_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P] = _txpwr_track_delta_swingidx_5ga_p,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N] = &_txpwr_track_delta_swingidx_2ga_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P] = &_txpwr_track_delta_swingidx_2ga_p,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N] = &_txpwr_track_delta_swingidx_2g_cck_a_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P] = &_txpwr_track_delta_swingidx_2g_cck_a_p,
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};
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const struct rtw89_rfe_parms rtw89_8851b_dflt_parms = {
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@@ -11,7 +11,7 @@ extern const struct rtw89_phy_table rtw89_8851b_phy_bb_table;
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extern const struct rtw89_phy_table rtw89_8851b_phy_bb_gain_table;
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extern const struct rtw89_phy_table rtw89_8851b_phy_radioa_table;
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extern const struct rtw89_phy_table rtw89_8851b_phy_nctl_table;
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extern const struct rtw89_txpwr_track_cfg rtw89_8851b_trk_cfg;
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extern const struct rtw89_fw_txpwr_track_cfg rtw89_8851b_trk_cfg;
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extern const struct rtw89_rfe_parms rtw89_8851b_dflt_parms;
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extern const struct rtw89_rfe_parms_conf rtw89_8851b_rfe_parms_conf[];
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@@ -2910,6 +2910,7 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
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} \
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__val; \
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})
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const struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
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struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
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u8 ch = chan->channel;
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u8 subband = chan->subband_type;
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@@ -2922,31 +2923,34 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
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u32 tmp = 0;
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u8 i, j;
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if (!trk)
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trk = &rtw89_8852a_trk_cfg;
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switch (subband) {
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default:
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case RTW89_CH_2G:
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thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_p;
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thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_2ga_n;
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thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_p;
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thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_2gb_n;
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
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thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
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thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
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break;
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case RTW89_CH_5G_BAND_1:
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thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[0];
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thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[0];
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thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[0];
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thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[0];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
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thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
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thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
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break;
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case RTW89_CH_5G_BAND_3:
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thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[1];
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thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[1];
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thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[1];
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thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[1];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
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thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
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thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
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break;
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case RTW89_CH_5G_BAND_4:
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thm_up_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_p[2];
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thm_down_a = rtw89_8852a_trk_cfg.delta_swingidx_5ga_n[2];
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thm_up_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_p[2];
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thm_down_b = rtw89_8852a_trk_cfg.delta_swingidx_5gb_n[2];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
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thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
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thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
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break;
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}
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@@ -2,6 +2,7 @@
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/* Copyright(c) 2019-2020 Realtek Corporation
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*/
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#include "fw.h"
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#include "phy.h"
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#include "reg.h"
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#include "rtw8852a_table.h"
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@@ -50983,19 +50984,19 @@ const struct rtw89_txpwr_table rtw89_8852a_byr_table = {
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.load = rtw89_phy_load_txpwr_byrate,
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};
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const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg = {
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.delta_swingidx_5gb_n = _txpwr_track_delta_swingidx_5gb_n,
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.delta_swingidx_5gb_p = _txpwr_track_delta_swingidx_5gb_p,
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.delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n,
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.delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p,
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.delta_swingidx_2gb_n = _txpwr_track_delta_swingidx_2gb_n,
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.delta_swingidx_2gb_p = _txpwr_track_delta_swingidx_2gb_p,
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.delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n,
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.delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p,
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.delta_swingidx_2g_cck_b_n = _txpwr_track_delta_swingidx_2g_cck_b_n,
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.delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p,
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.delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n,
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.delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
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const struct rtw89_fw_txpwr_track_cfg rtw89_8852a_trk_cfg = {
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.delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N] = _txpwr_track_delta_swingidx_5gb_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P] = _txpwr_track_delta_swingidx_5gb_p,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N] = _txpwr_track_delta_swingidx_5ga_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P] = _txpwr_track_delta_swingidx_5ga_p,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N] = &_txpwr_track_delta_swingidx_2gb_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P] = &_txpwr_track_delta_swingidx_2gb_p,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N] = &_txpwr_track_delta_swingidx_2ga_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P] = &_txpwr_track_delta_swingidx_2ga_p,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N] = &_txpwr_track_delta_swingidx_2g_cck_b_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P] = &_txpwr_track_delta_swingidx_2g_cck_b_p,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N] = &_txpwr_track_delta_swingidx_2g_cck_a_n,
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.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P] = &_txpwr_track_delta_swingidx_2g_cck_a_p,
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};
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const struct rtw89_rfe_parms rtw89_8852a_dflt_parms = {
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@@ -11,7 +11,7 @@ extern const struct rtw89_phy_table rtw89_8852a_phy_bb_table;
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extern const struct rtw89_phy_table rtw89_8852a_phy_radioa_table;
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extern const struct rtw89_phy_table rtw89_8852a_phy_radiob_table;
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extern const struct rtw89_phy_table rtw89_8852a_phy_nctl_table;
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extern const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg;
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extern const struct rtw89_fw_txpwr_track_cfg rtw89_8852a_trk_cfg;
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extern const struct rtw89_rfe_parms rtw89_8852a_dflt_parms;
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#endif
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@@ -2784,6 +2784,7 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
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} \
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__val; \
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})
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const struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
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struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
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u8 ch = chan->channel;
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u8 subband = chan->subband_type;
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@@ -2796,31 +2797,34 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
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u32 tmp = 0;
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u8 i, j;
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if (!trk)
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trk = &rtw89_8852b_trk_cfg;
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switch (subband) {
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default:
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case RTW89_CH_2G:
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thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_2ga_p;
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thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_2ga_n;
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thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_2gb_p;
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thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_2gb_n;
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
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thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
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thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
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break;
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case RTW89_CH_5G_BAND_1:
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thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[0];
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thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[0];
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thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[0];
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thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[0];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
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thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
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thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
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thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
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break;
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case RTW89_CH_5G_BAND_3:
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thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[1];
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thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[1];
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thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[1];
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thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[1];
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thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
|
||||
break;
|
||||
case RTW89_CH_5G_BAND_4:
|
||||
thm_up_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_p[2];
|
||||
thm_down_a = rtw89_8852b_trk_cfg.delta_swingidx_5ga_n[2];
|
||||
thm_up_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_p[2];
|
||||
thm_down_b = rtw89_8852b_trk_cfg.delta_swingidx_5gb_n[2];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
/* Copyright(c) 2019-2020 Realtek Corporation
|
||||
*/
|
||||
|
||||
#include "fw.h"
|
||||
#include "phy.h"
|
||||
#include "reg.h"
|
||||
#include "rtw8852b_table.h"
|
||||
@@ -22895,19 +22896,19 @@ const struct rtw89_txpwr_table rtw89_8852b_byr_table = {
|
||||
.load = rtw89_phy_load_txpwr_byrate,
|
||||
};
|
||||
|
||||
const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg = {
|
||||
.delta_swingidx_5gb_n = _txpwr_track_delta_swingidx_5gb_n,
|
||||
.delta_swingidx_5gb_p = _txpwr_track_delta_swingidx_5gb_p,
|
||||
.delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n,
|
||||
.delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p,
|
||||
.delta_swingidx_2gb_n = _txpwr_track_delta_swingidx_2gb_n,
|
||||
.delta_swingidx_2gb_p = _txpwr_track_delta_swingidx_2gb_p,
|
||||
.delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n,
|
||||
.delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p,
|
||||
.delta_swingidx_2g_cck_b_n = _txpwr_track_delta_swingidx_2g_cck_b_n,
|
||||
.delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p,
|
||||
.delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n,
|
||||
.delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
|
||||
const struct rtw89_fw_txpwr_track_cfg rtw89_8852b_trk_cfg = {
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N] = _txpwr_track_delta_swingidx_5gb_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P] = _txpwr_track_delta_swingidx_5gb_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N] = _txpwr_track_delta_swingidx_5ga_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P] = _txpwr_track_delta_swingidx_5ga_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N] = &_txpwr_track_delta_swingidx_2gb_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P] = &_txpwr_track_delta_swingidx_2gb_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N] = &_txpwr_track_delta_swingidx_2ga_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P] = &_txpwr_track_delta_swingidx_2ga_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N] = &_txpwr_track_delta_swingidx_2g_cck_b_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P] = &_txpwr_track_delta_swingidx_2g_cck_b_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N] = &_txpwr_track_delta_swingidx_2g_cck_a_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P] = &_txpwr_track_delta_swingidx_2g_cck_a_p,
|
||||
};
|
||||
|
||||
const struct rtw89_rfe_parms rtw89_8852b_dflt_parms = {
|
||||
|
||||
@@ -12,7 +12,7 @@ extern const struct rtw89_phy_table rtw89_8852b_phy_bb_gain_table;
|
||||
extern const struct rtw89_phy_table rtw89_8852b_phy_radioa_table;
|
||||
extern const struct rtw89_phy_table rtw89_8852b_phy_radiob_table;
|
||||
extern const struct rtw89_phy_table rtw89_8852b_phy_nctl_table;
|
||||
extern const struct rtw89_txpwr_track_cfg rtw89_8852b_trk_cfg;
|
||||
extern const struct rtw89_fw_txpwr_track_cfg rtw89_8852b_trk_cfg;
|
||||
extern const struct rtw89_rfe_parms rtw89_8852b_dflt_parms;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -2992,7 +2992,7 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
|
||||
} \
|
||||
__val; \
|
||||
})
|
||||
struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
|
||||
const struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
|
||||
struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
|
||||
u8 ch = chan->channel;
|
||||
u8 subband = chan->subband_type;
|
||||
@@ -3005,91 +3005,62 @@ static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx ph
|
||||
u32 tmp = 0;
|
||||
u8 i, j;
|
||||
|
||||
if (!trk)
|
||||
trk = &rtw89_8852c_trk_cfg;
|
||||
|
||||
switch (subband) {
|
||||
default:
|
||||
case RTW89_CH_2G:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_2ga_p;
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_2ga_n;
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_2gb_p;
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_2gb_n;
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
|
||||
break;
|
||||
case RTW89_CH_5G_BAND_1:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5ga_p[0];
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5ga_n[0];
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5gb_p[0];
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5gb_n[0];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
|
||||
break;
|
||||
case RTW89_CH_5G_BAND_3:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5ga_p[1];
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5ga_n[1];
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5gb_p[1];
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5gb_n[1];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
|
||||
break;
|
||||
case RTW89_CH_5G_BAND_4:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5ga_p[2];
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5ga_n[2];
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5gb_p[2];
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_5gb_n[2];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
|
||||
break;
|
||||
case RTW89_CH_6G_BAND_IDX0:
|
||||
case RTW89_CH_6G_BAND_IDX1:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[0];
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[0];
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[0];
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[0];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
|
||||
break;
|
||||
case RTW89_CH_6G_BAND_IDX2:
|
||||
case RTW89_CH_6G_BAND_IDX3:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[1];
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[1];
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[1];
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[1];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
|
||||
break;
|
||||
case RTW89_CH_6G_BAND_IDX4:
|
||||
case RTW89_CH_6G_BAND_IDX5:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[2];
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[2];
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[2];
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[2];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
|
||||
break;
|
||||
case RTW89_CH_6G_BAND_IDX6:
|
||||
case RTW89_CH_6G_BAND_IDX7:
|
||||
thm_up_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_p[3];
|
||||
thm_down_a = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6ga_n[3];
|
||||
thm_up_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_p[3];
|
||||
thm_down_b = trk ? trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3] :
|
||||
rtw89_8852c_trk_cfg.delta_swingidx_6gb_n[3];
|
||||
thm_up_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
|
||||
thm_down_a = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
|
||||
thm_up_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
|
||||
thm_down_b = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
/* Copyright(c) 2019-2022 Realtek Corporation
|
||||
*/
|
||||
|
||||
#include "fw.h"
|
||||
#include "phy.h"
|
||||
#include "reg.h"
|
||||
#include "rtw8852c_table.h"
|
||||
@@ -57109,23 +57110,23 @@ const struct rtw89_txpwr_table rtw89_8852c_byr_table = {
|
||||
.load = rtw89_phy_load_txpwr_byrate,
|
||||
};
|
||||
|
||||
const struct rtw89_txpwr_track_cfg rtw89_8852c_trk_cfg = {
|
||||
.delta_swingidx_6gb_n = _txpwr_track_delta_swingidx_6gb_n,
|
||||
.delta_swingidx_6gb_p = _txpwr_track_delta_swingidx_6gb_p,
|
||||
.delta_swingidx_6ga_n = _txpwr_track_delta_swingidx_6ga_n,
|
||||
.delta_swingidx_6ga_p = _txpwr_track_delta_swingidx_6ga_p,
|
||||
.delta_swingidx_5gb_n = _txpwr_track_delta_swingidx_5gb_n,
|
||||
.delta_swingidx_5gb_p = _txpwr_track_delta_swingidx_5gb_p,
|
||||
.delta_swingidx_5ga_n = _txpwr_track_delta_swingidx_5ga_n,
|
||||
.delta_swingidx_5ga_p = _txpwr_track_delta_swingidx_5ga_p,
|
||||
.delta_swingidx_2gb_n = _txpwr_track_delta_swingidx_2gb_n,
|
||||
.delta_swingidx_2gb_p = _txpwr_track_delta_swingidx_2gb_p,
|
||||
.delta_swingidx_2ga_n = _txpwr_track_delta_swingidx_2ga_n,
|
||||
.delta_swingidx_2ga_p = _txpwr_track_delta_swingidx_2ga_p,
|
||||
.delta_swingidx_2g_cck_b_n = _txpwr_track_delta_swingidx_2g_cck_b_n,
|
||||
.delta_swingidx_2g_cck_b_p = _txpwr_track_delta_swingidx_2g_cck_b_p,
|
||||
.delta_swingidx_2g_cck_a_n = _txpwr_track_delta_swingidx_2g_cck_a_n,
|
||||
.delta_swingidx_2g_cck_a_p = _txpwr_track_delta_swingidx_2g_cck_a_p,
|
||||
const struct rtw89_fw_txpwr_track_cfg rtw89_8852c_trk_cfg = {
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N] = _txpwr_track_delta_swingidx_6gb_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P] = _txpwr_track_delta_swingidx_6gb_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N] = _txpwr_track_delta_swingidx_6ga_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P] = _txpwr_track_delta_swingidx_6ga_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N] = _txpwr_track_delta_swingidx_5gb_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P] = _txpwr_track_delta_swingidx_5gb_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N] = _txpwr_track_delta_swingidx_5ga_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P] = _txpwr_track_delta_swingidx_5ga_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N] = &_txpwr_track_delta_swingidx_2gb_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P] = &_txpwr_track_delta_swingidx_2gb_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N] = &_txpwr_track_delta_swingidx_2ga_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P] = &_txpwr_track_delta_swingidx_2ga_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N] = &_txpwr_track_delta_swingidx_2g_cck_b_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P] = &_txpwr_track_delta_swingidx_2g_cck_b_p,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N] = &_txpwr_track_delta_swingidx_2g_cck_a_n,
|
||||
.delta[RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P] = &_txpwr_track_delta_swingidx_2g_cck_a_p,
|
||||
};
|
||||
|
||||
const struct rtw89_phy_tssi_dbw_table rtw89_8852c_tssi_dbw_table = {
|
||||
|
||||
@@ -13,7 +13,7 @@ extern const struct rtw89_phy_table rtw89_8852c_phy_radioa_table;
|
||||
extern const struct rtw89_phy_table rtw89_8852c_phy_radiob_table;
|
||||
extern const struct rtw89_phy_table rtw89_8852c_phy_nctl_table;
|
||||
extern const struct rtw89_phy_tssi_dbw_table rtw89_8852c_tssi_dbw_table;
|
||||
extern const struct rtw89_txpwr_track_cfg rtw89_8852c_trk_cfg;
|
||||
extern const struct rtw89_fw_txpwr_track_cfg rtw89_8852c_trk_cfg;
|
||||
extern const struct rtw89_rfe_parms rtw89_8852c_dflt_parms;
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user